Non-volatile memory devices

Claim 2

A memory device comprising: A. a field effect transistor having a source region and a drain region separated by a channel, and a floating gate electrode disposed above the channel and separated therefrom by a gate insulating layer; B. a capacitance disposed between the floating gate and a controlled potential thereby permitting the storage of a charge on the floating gate, the capacitance being shielded from exposure to any illuminating radiation; C. illuminating means for exposing the transistor to radiation thereby rendering the insulating layer conductive during the exposure; D. writing means for altering the charge on the floating gate during operation of the illuminating means; and E. reading means for detecting the presence of charge on the floating gate.

Claim 3

The device of claim 1 wherein said illumination means is a source of ultraviolet radiation.

Claim 4

The device of claim 1 wherein the capacitance is further defined by a capacitor formed by a second insulating layer disposed between the floating gate and a region maintained at a fixed potential.

Claim 5

The device of claim 1 wherein the capacitance is further defined by a capacitor formed by a second insulating layer disposed between the floating gate and a conductive line of variable electrical potential.

Claim 6

The device of claim 1 wherein said source and drain of said transistor are connected together.

Claim 7

The device of claim 1 wherein said writing means further includes a SET input line and a RESET input line; the SET line and the floating gate electrode serving as inputs to a first NOR gate; the output of the first NOR gate and the RESET input line serving as inputs to a second NOR gate; and the output of said second NOR gate being connected to the source of said memory device, whereby the cascading arrangement of said first and second NOR gates permit a user to program a binary "1" value on the floating gate by raising only the SET line, to program a binary "0" value on the floating gating by raising only the RESET line, and to retain the previous value of the floating gate whenever both the SET and RESET lines are low.

Claim 8

The device of claim 6 wherein each of said NOR gates is implemented by a depletion mode pull-up transistor in conjunction with two parallel, enhancement mode pull-down transistors.

Claim 9

The device of claim 6 wherein the output of said second NOR gate also comprises the reading means of said device.

Claim 10

An array of memory cells, the array comprising a plurality of memory devices according to claim 1; and selective activation means for activity the writing means of said individual memory devices.

Claim 11

The array of claim 9 wherein a single illumination means serves to illuminate the floating gates of the plurality of memory devices during the operation of their writing means.

Claim 12

A combination memory device employing both volatile and non-volatile memory elements to permit parallel writing of such devices in an array configuration, the combination device comprising: A. a static random access memory cell formed by a cross-coupled, bistable, register circuit and means for latching said cell into one of its bistable states; B. a field effect transistor having a source region and a drain region separated by a channel, and a floating gate electrode disposed above the channel and separated therefrom by an insulating layer; C. a capacitance disposed between the floating gate and a controlled potential thereby permitting the storage of a charge on the floating gate, the capacitance being shielded from exposure to radiation; D. illuminating means for exposing the transistor to radiation thereby rendering the gate insulating layer conductive during exposure; E. writing means for altering the charge on the floating gate during operation of the illumination means and in response to the state of the static memory cell; and F. reading means for detecting the presence of charge on the floating gate.

Claim 13

A combination memory device employing both volatile and non-volatile memory elements to permit parallel writing of such devices in an array configuration, the combination device comprising: A. a static random access memory cell formed by a cross-coupled, bistable, register circuit and means for latching said cell into one of its bistable states; B. a field effect transistor having a source region and a drain region separated by a channel, and a floating gate electrode disposed above the channel and separated therefrom by an insulating layer; C. a capacitance disposed between the floating gate and a controlled potential thereby permitting the storage of a charge on the floating gate, the capacitance being shielded from exposure to radiation; D. illuminating means for exposing the transistor to radiation thereby rendering the gate insulating layer conductive during exposure; E. writing means for altering the charge on the floating gate during operation of the illumination means and in response to the state of the static memory cell; and F. reading means for detecting the presence of charge on the floating gate.