Semiconductor memories

Claim 2

A semiconductor static random access memory, including a plurality of memory cells each having first and second field effect transistors cross-coupled to form a flip-flop circuit, the cells being disposed in an array of rows on a semiconductor substrate, and word lines and bit lines whereby, in use, the cells of the array are accessed, wherein each cell comprises first and second end regions and a central region, the end regions being mutually displaced in the row direction, wherein the gate of the second transistor has a first portion perpendicular to the row direction and a second portion generally at an angle to the first portion, and wherein the gate of the first transistor is disposed generally parallel to the second portion of the gate of the second transistor.

Claim 3

A memory as claimed in claim 1 wherein the cells are disposed in rows of mirror image pairs of cells whereby the cells are tessellated on the substrate.

Claim 4

A semiconductor static random access memory, including a plurality of memory cells each having first and second field effect transistors cross-coupled to form a flip-flop circuit, the cells being disposed in an array of rows on a semiconductor substrate, and word lines and bit lines whereby, in use, the cells of the array are accessed, wherein the gate of the second transistor has a first portion transverse to the row direction and a second portion generally at an angle to the first portion, wherein the gate of the first transistor is disposed parallel to the second portion of the second transistor gate, and wherein the cell transistors are so arranged that a route is provided between adjacent rows of cells and within which route a straighter word line is accommodated than can be provided in a corresponding cell not having transistors with gates or gate portions disposed at an angle to the transverse to the row direction.

Claim 5

A semiconductor static random access memory, including a plurality of memory cells each having first and second field effect transistors cross-coupled to form a flip-flop circuit, the cells being disposed in an array of rows on a semiconductor substrate, and word lines and bit lines whereby, in use, the cells of the array are accessed, wherein the gate of the second transistor has a first portion transverse to the row direction and a second portion generally at an angle to the first portion, wherein the gate of the first transistor is disposed parallel to the second portion of the second transistor gate, and wherein the cell transistors are so arranged that a route is provided between adjacent rows of cells and within which route a straighter word line is accommodated than can be provided in a corresponding cell not having transistors with gates or gate portions disposed at an angle to the transverse to the row direction.

Claim 6

A memory as claimed in claim 3, wherein the word line comprises polycrystalline silicon.

Claim 7

A memory as claimed in claim 4, wherein the memory cells are disposed in two similar array portions, each said word line extending across only one said array portion.

Claim 8

In a semiconductor random access memory having an array of rows of cells each including first and second field effect storage to resistors cross coupled in a flip-flop configuration, and first and second access transistors coupled to the drains of the respective storage transistors, each cell being accessible via a pair of bit lines and a polysilicon word line, said word line being coupled to the gates of the access transistors, the improvement comprising: a memory cell configuration wherein each said cell comprises first and second end regions disposed in a first direction generally perpendicular to the row direction and a central region disposed in a second direction generally at an angle to the perpendicular to the row direction, wherein the gate of the first storage transistor is disposed parallel to the second direction, and wherein the gate of the second storage transistor has a first portion parallel to the first direction and a second portion parallel to the second direction whereby the configuration of the cell is such as to permit at least a substantial reduction in the degree of convolution of the word line, thereby reducing the electrical resistance of the word line.

Claim 9

In a semiconductor random access memory having an array of rows of cells each including first and second field effect storage to resistors cross coupled in a flip-flop configuration, and first and second access transistors coupled to the drains of the respective storage transistors, each cell being accessible via a pair of bit lines and a polysilicon word line, said word line being coupled to the gates of the access transistors, the improvement comprising: a memory cell configuration wherein each said cell comprises first and second end regions disposed in a first direction generally perpendicular to the row direction and a central region disposed in a second direction generally at an angle to the perpendicular to the row direction, wherein the gate of the first storage transistor is disposed parallel to the second direction, and wherein the gate of the second storage transistor has a first portion parallel to the first direction and a second portion parallel to the second direction whereby the configuration of the cell is such as to permit at least a substantial reduction in the degree of convolution of the word line, thereby reducing the electrical resistance of the word line.

Claim 10

A memory as claimed in claim 6 wherein the cells are disposed in rows of mirror image pairs of cells whereby the cells are tessellated on the substrate.