US4584671A
Expired / Lapsed
US
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Semiconductor memories
Assignee: STC PLC
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Filing: 1983-12-02
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Granted: 1986-04-22
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Expires: 2003-12-02
Abstract
Abstract The cells of a static random access memory have a diagonal of `dog leg` structural layout. This permits the use of straight word lines of low impedance and hence of low time constant. Advantageously the work lines are of polysilicon thus permitting a compact design.
Inventors
- 👤 Trevor K. Monk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:37
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H10; H10B; H10B10/00; H10B10/15
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
180 words
A semiconductor static random access memory, including a plurality of memory cells each having first and second field effect transistors cross-coupled to form a flip-flop circuit, the cells being disposed in a rectangular array or rows and columns on a semiconductor substrate, word lines one for each row of said memory cells, and bit lines one for each column of said memory cells, wherein each memory cell comprises first and second end portions arranged parallel to the array columns, and a central portion arranged at an angle to the end portions so as to provide the cell with a dog leg configuration, wherein the gate of the first transistor is disposed parallel to the central portion of the cell, wherein the gates of the second transistor has a first portion parallel to an end portion of the cell and a second portion parallel to the central portion of the cell, and wherein the two transistors are so disposed within the cell that a straight route is provided for the word line across the cells of each row of the array.
Claim 2
Dependent Claim
180 words
A semiconductor static random access memory, including a plurality of memory cells each having first and second field effect transistors cross-coupled to form a flip-flop circuit, the cells being disposed in a rectangular array or rows and columns on a semiconductor substrate, word lines one for each row of said memory cells, and bit lines one for each column of said memory cells, wherein each memory cell comprises first and second end portions arranged parallel to the array columns, and a central portion arranged at an angle to the end portions so as to provide the cell with a dog leg configuration, wherein the gate of the first transistor is disposed parallel to the central portion of the cell, wherein the gates of the second transistor has a first portion parallel to an end portion of the cell and a second portion parallel to the central portion of the cell, and wherein the two transistors are so disposed within the cell that a straight route is provided for the word line across the cells of each row of the array.
Claim 3
Dependent Claim
18 words
A memory as claimed in claim 1, wherein the word lines and bit lines comprise polycrystalline silicon tracks.
Claim 4
Dependent Claim
18 words
A memory as claimed in claim 2 wherein said bit line and word line tracks are mutually perpendicular.
Claim 5
Dependent Claim
15 words
A memory as claimed in claim 1 and fabricated by an NMOS or HMOS process.
Claim 6
Dependent Claim
28 words
A memory as claimed in claim 1, wherein the memory cells are disposed in two similar arrays, each said word line extending across only one of said arrays.
Claim 7
Dependent Claim
13 words
A calculating device including a plurality of memories as claimed in claim 1.
References Cited (Backward Citations)
US4420820A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |