Display architecture having variable data width

Claim 1

A display architecture of memory chips for supplying scan line data to a display screen, said display architecture allowing a variable, selectable number of bits per chip and a variable, selectable segment width defining a full scan line on said display screen, comprising: a plurality of dynamic memory chips, each of said chips including at least first and second data islands, each island having its own data in/out line, chip select line, and increment bit line, said chips being arranged from a lowest order chip to a highest order chip and addressable by a physical bit address b o and a physical word address w o ; processor means for generating a starting row and column address X o ,Y o of data to be supplied to said display screen, a segment width S, and a data path width N D equal to a maximum number of pels per line divided by the number of bits per segment; and function generator means for supplying signals to the data in/out lines, chip select lines, and increment bit lines of said dynamic memory chips, said function generator means being connected to said processor means to derive the word address w o and an island address bit from the starting column address Y o and to generate the bit address b o as the integer portion of the quotient of the starting row address X o divided by N D , the highest order bits of said bit address b o being determined by the segment width S and a segment of a physical word line s o derived from the highest order bits of the starting column address Y o , said function generator means including bit incrementing means for computing the bit increment A I =N D -(X o +N f ), where N f is a data field of variable width, and bit incrementer and carry propagate means on each of said chips for modifying the physical bit address b o to an actual bit address for that particular chip, said function generator means further including spill/wrap control means connected to said bit incrementer and carry propagate means for controlling the carry propagation of the high order bits of the actual bit address to cause the bit address to wrap to the first bit of the same segment, but only on that chip, when the sign of A I is negative and the address bits for that segment are all 1's.