Patent US4663543A successfully refreshed from Google Patents.
US4663543A
Expired / Lapsed
US
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Voltage level shifting depletion mode FET logical circuit
Assignee: Nortel Networks Ltd
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Filing: 1985-09-19
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Granted: 1987-05-05
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Expires: 2005-09-19
Abstract
Abstract A GaAs D-MESFET logic system having a low power delay product has a switching second and a voltage level shifting section. The voltage level shifting section consists of a chain of diodes and a pulldown transistor. The switching section consists of an array of D-MESFETs which acts to speed up operation of a coupling capacitor. The low power dissipation of known capacitor coupled D-MESFET logic is thus preserved, while reducing gate delay.
Inventors
- 👤 John E. Sitch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
152 words
A logic cell using depletion-MESFETs, the cell comprising: a driver section, a voltage level shifting section series connected to an output of the driver section, and a coupling capacitor connected in shunt with the voltage level shifting section; the driver section implemented as an array of depletion-MESFETs and having a switching section and a timing section, the timing section having a higher switching speed than that of the switching section; the switching section operable in response to a logic input level to give a corresponding logic output level to the voltage level shifting section; the timing section operable to control the switching section so that during the period of a logic swing in a first direction current flows from the coupling capacitor to a low reference voltage point, and during the period of a logic swing in the opposite direction current flows from a high reference voltage point to the coupling capacitor.
Claim 2
Dependent Claim
152 words
A logic cell using depletion-MESFETs, the cell comprising: a driver section, a voltage level shifting section series connected to an output of the driver section, and a coupling capacitor connected in shunt with the voltage level shifting section; the driver section implemented as an array of depletion-MESFETs and having a switching section and a timing section, the timing section having a higher switching speed than that of the switching section; the switching section operable in response to a logic input level to give a corresponding logic output level to the voltage level shifting section; the timing section operable to control the switching section so that during the period of a logic swing in a first direction current flows from the coupling capacitor to a low reference voltage point, and during the period of a logic swing in the opposite direction current flows from a high reference voltage point to the coupling capacitor.
Claim 3
Dependent Claim
45 words
A logic cell as claimed in claim 1 in which said switching section comprises a pair of depletion-MESFETs series conected between the high reference voltage point and the low reference voltage point, the driver section output being taken from the junction between the two depletion-MESFETs.
Claim 4
Dependent Claim
75 words
A logic cell as claimed in claim 2 in which the timing section comprises a further pair of depletion-MESFETs series connected between the high and low reference voltage points, a logic input being applied commonly to gates of the depletion-MESFETs connected to the low reference voltage, the gates of the depletion-MESFETs connected to the high reference voltage point being connected to the source of that timing section depletion-MESFET connected to the high reference voltage point.
Claim 5
Dependent Claim
23 words
A logic cell as claimed in claim 3 wherein the depletion-MESFETs connected to the low reference voltage point comprise a single split-gate device.
Claim 6
Dependent Claim
23 words
A logic cell as claimed in claim 3 wherein the depletion-MESFETs connected to the high reference voltage point comprise a single split-gate device.
Claim 7
Dependent Claim
64 words
A logic cell as claimed in claim 3 wherein the timing section that is connected to the high reference voltage point has its source connected to the switching section depletion-MESFET connected to the high reference voltage point and has its gate connected to the source and gate of a further depletion-MESFET, the further depletion-MESFET having its drain connected to the high reference voltage point.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-04 | 1990-11-03 | 1991-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-04 | 1994-11-03 | 1995-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-04 | 1998-11-03 | 1999-05-05 | $7700.00 | Window Closed / Lapsed |