US4660143A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable realtime interface between a Block Floating Point processor and memory
Assignee: United States Department of the Air Force
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Filing: 1984-09-24
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Granted: 1987-04-21
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Expires: 2004-09-24
Abstract
Abstract The programmable interface gives a Block Floating Point processor the capability of performing various real-time signal algorithms on collected radar data in an external batch memory. Normally, Block Floating Point processors are not capable of accommodating data having varying exponent scales such as the data received from a batch memory in a radar system. The programmable interface solves the exponential normalization process using two data paths, an instruction processor, a microcode processor, a pre-shift control and an address generator. Data flow instructions are passed from the instruction processor to the microcode processor which executes the particular instruction's timing sequence. The first data path passes data from the batch memory to the array processor and contains a pre-shifter to normalize the batch memory-stored data. The second data path passes the processed data from the processor to the batch memory. The pre-shifter portion of the first data path is controlled by a pre-shifter control section in the invention, which generates a 4-bit code used to command the pre-shifter. Finally, an address generator creates a sequence of fetch and store addresses for data travelling between the batch memory and the array processor.
Inventors
- 👤 Thomas M. King
- 👤 Sam M. Daniel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/295; G06F5/00; G06F5/01; G06F5/012
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
394 words
In combination with a data processing system having a batch memory which receives data signals, and a data processor receiving and processing a group of control and address signals and said data signals, and a control system for giving instruction signals to said data processing system, an interface between said batch memory and said data processor, said interface comprising: an instruction processor means performing a sequence of fetch and store operations by receiving a first control and address signal from said batch memory and said instruction signals from said control system and outputting a second control and address signal; a microcode processor means receiving said second control and address signal from said instruction processor means and said instruction signals from said control system and outputting a third control and address signal to said data processor, said third control and address signal controlling fetch and store operations of said data processor as modified by said control system; a pre-shifter control means receiving a fourth control and address signal from said processor and generating a pre-shifter control signal which controls all exponential normalization of said data signals; a first amplifier receiving and amplifying said data signals from said batch memory and producing an output signal; a first flip flop producing an output signal by processing said output signal from said first amplifier; a pre-shifter means receiving said output signal from said first flip flop and said pre-shifter control signal from said pre-shifter control means and producing an exponentially normalized data signal; a second flip flop producing an output signal by processing said exponentially normalized data signal from said pre-shifter means; a first multiplexer producing an output signal by multiplexing said output signal from said second flip flop with said instruction signals from said control system; a bus transmitter producing an output signal for said data processor by amplifying said output signal from said first multiplexer; a data path relaying processed data signals from said data processor to said batch memory; and an address generator means outputting address signals to said batch memory and said pre-shifter control means, said address signals containing a first memory address for said data signals fetched from said batch memory on said first data path, said address signals containing a second memory address for said processed data signals transferred from said data processor to said batch memory by said second data path.
Claim 2
Dependent Claim
394 words
In combination with a data processing system having a batch memory which receives data signals, and a data processor receiving and processing a group of control and address signals and said data signals, and a control system for giving instruction signals to said data processing system, an interface between said batch memory and said data processor, said interface comprising: an instruction processor means performing a sequence of fetch and store operations by receiving a first control and address signal from said batch memory and said instruction signals from said control system and outputting a second control and address signal; a microcode processor means receiving said second control and address signal from said instruction processor means and said instruction signals from said control system and outputting a third control and address signal to said data processor, said third control and address signal controlling fetch and store operations of said data processor as modified by said control system; a pre-shifter control means receiving a fourth control and address signal from said processor and generating a pre-shifter control signal which controls all exponential normalization of said data signals; a first amplifier receiving and amplifying said data signals from said batch memory and producing an output signal; a first flip flop producing an output signal by processing said output signal from said first amplifier; a pre-shifter means receiving said output signal from said first flip flop and said pre-shifter control signal from said pre-shifter control means and producing an exponentially normalized data signal; a second flip flop producing an output signal by processing said exponentially normalized data signal from said pre-shifter means; a first multiplexer producing an output signal by multiplexing said output signal from said second flip flop with said instruction signals from said control system; a bus transmitter producing an output signal for said data processor by amplifying said output signal from said first multiplexer; a data path relaying processed data signals from said data processor to said batch memory; and an address generator means outputting address signals to said batch memory and said pre-shifter control means, said address signals containing a first memory address for said data signals fetched from said batch memory on said first data path, said address signals containing a second memory address for said processed data signals transferred from said data processor to said batch memory by said second data path.
Claim 3
Dependent Claim
95 words
An interface as defined in claim 1 wherein said instruction processor means comprises: a first microcode sequence generator producing an output signal by receiving and microcoding said first control and address signal from said batch memory; a first memory means receiving and storing said instruction signals from said control system and said output signal from said first microcode sequence generator and producing an output signal; and a decoder means outputting said second control and address signal by processing said output signal from said first memory means with said instruction signals received from said control system.
Claim 4
Dependent Claim
99 words
An interface as defined in claim 2 wherein said microcode processor means comprises: a second microcode sequence generator producing an output signal by receiving and microcoding said second control and address signal from said instruction processor means with a fifth control and address signal from said data processor; a second memory means receiving and storing said instruction signals from said control system and said output signal from said second microcode sequence generator and producing an output signal; and a third flip flop outputting said third control and address signal by processing said output signal from said second memory means.
Claim 5
Dependent Claim
120 words
An interface as defined in claim 3 wherein said pre-shifter control means comprises: a comparator means producing an output signal by receiving and comparing said fourth control and address signal from said data processor with a comparison signal produced in said pre-shifter control means; a fourth flip flop producing said comparison signal by processing said output signal from said comparator means; a third memory means receiving said fourth control and address signal from said data processor and said address signals from said address generator means and producing an output signal; and a subtractor means producing said pre-shifter control signal by subtracting said output signal received from said third memory means from said comparison signal received from said fourth flip flop.
Claim 6
Dependent Claim
146 words
An interface as defined in claim 4 wherein said address generator comprises: a second multiplexer producing an output signal by multiplexing said address signals produced by said address generator with said third control and address signal produced by said microcode processor means; a register means receiving said output signal from said second multiplexer and producing an incremented register signal; a third multiplexer producing an output signal by multiplexing said incremented register signal from said register means with said third control and address signal produced by said microcode processor means; a fourth multiplexer producing an output signal by multiplexing said address signals produced by said address generator with said third control and address signal produced by said microcode processor means; and a first arithmetic logic unit outputting said address signals by processing said output signal from said third multiplexer with said output signal from said fourth multiplexer.
Claim 7
Dependent Claim
38 words
An interface as defined in claim 5 wherein said address generator includes: a second amplifier producing and sending to said batch memory amplified address signals by receiving and amplifying said address signals from said first arithmetic logic unit.
Claim 8
Dependent Claim
36 words
An interface as defined in claim 6 wherein said register means of said address generator comprises: a fifth flip flop producing said incremented register signal by receiving and processing said output signal from said second multiplexer.
Claim 9
Dependent Claim
49 words
An interface as defined in claim 7 wherein said subtractor means in said pre-shifter control means is a second arithmetic logic unit which produces said pre-shifter control signal by subtracting said output signal received from said third memory means from said comparison signal received from said fourth flip flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-20 | 1990-10-20 | 1991-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-20 | 1994-10-20 | 1995-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-20 | 1998-10-20 | 1999-04-21 | $7700.00 | Window Closed / Lapsed |