Complementary MOS integrated circuit having means for preventing latch-up phenomenon

Claim 1

A MOS integrated circuit comprising: a semi-conductor substrate of one conductivity type; a well-region of another conductivity type formed in said semi-conductor substrate; a first MOS field effect transistor of a first channel type formed in said well-region, said first MOS field effect transistor having source and drain regions of said one conductivity type; a second MOS field effect transistor of another channel type formed in said semi-conductor substrate outside said well region, said second MOS field effect transistor having source and drain regions of said another conductivity type; a high impurity region formed in said well region and having said another conductivity type, said high impurity region surrounding said first MOS field effect transistor; a first insulator film covering said semiconductor substrate, said well-region, said first and second MOS field effect transistors and said high impurity region, said first insulator film having first holes exposing first contact portions of said drain regions in said first and second MOS field effect transistors and a plurality of second holes exposing a plurality of second contact portions of said high impurity region, said second holes being arranged to substantially surround said first MOS field effect transistor; first wiring layers covering said first insulator film and connected with said first contact portions through said first holes; a second wiring layer covering said first insulator film and connected with said second contact portions through said second holes, said second wiring layer substantially surrounding said first MOS field effect transistor; a second insulator film covering said first and second wiring layers and having third holes exposing third contact portions of said first wiring layers and a plurality of fourth holes exposing a plurality of fourth contact portions of said second wiring layer, said fourth holes being arranged to substantially surround said first MOS field effect transistor; a third wiring layer covering said second insulator film and connected with said third contact portions through said third holes, said third wiring layer crossing said high impurity region and interconnecting said first and second MOS field effect transistors to form an electrical circuit; a fourth wiring layer covering said second insulator film and connected with said fourth contact portions through said fourth holes, said fourth wiring layer substantially surrounding said first MOS field effect transistor; and a means for supplying a constant potential to said fourth wiring layer.