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US4658399A
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Circuit arrangement designed to pick up the error rate in numerical transmission systems
Assignee: Italtel SpA
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Filing: 1984-12-20
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Granted: 1987-04-14
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Expires: 2004-12-20
Abstract
Abstract A circuit arrangement for detecting the error rate (BER) in numerical transmission systems which use a line code of the 1B/2B type. The circuit arrangement includes the presence of means (MS) to output respectively a first and a second bit stream (A and B) obtained by serializing respectively the first and the second bits of the words making up the input stream. The streams (A and B) are input respectively into the first and second means for detecting errors (PRE and SRE) designed to activate their own outputs when they detect the presence of pairs of bits that are respectively "1--1" and "0--0". Furthermore, it includes the presence of error-totalling means (TE) connected to the outputs of the first and second means for detecting errors.
Inventors
- 👤 Aldo D'Angio
- 👤 Claudio Regola
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:04
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24; H04L1/245; H04L1/246
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
194 words
A circuit arrangement for measuring an error rate in a numerical transmission system using a 1B/2B line code in which each symbol of an original code is converted into a train of two-bit words including a first bit of one of two binary values and a second bit of one of said two binary values, said circuit arrangement comprising: separating means having an input receiving said train of two-bit words and first and second outputs, said first output generating a first stream of said first bits in serialized form from said train of two-bit words, said second output generating a second stream of said second bits in serialized form corresponding to said train of two-bit words; first detecting means connected to said first output and responsive to the appearance of consecutive first bits of one of said binary values for generating an output representing an error count; second means connected with said second output and responsive to consecutive second bits of the other of said binary values for generating an output representing an error count; and counting means connected to outputs of said first and second means for totaling said counts representing said errors.
Claim 2
Dependent Claim
194 words
A circuit arrangement for measuring an error rate in a numerical transmission system using a 1B/2B line code in which each symbol of an original code is converted into a train of two-bit words including a first bit of one of two binary values and a second bit of one of said two binary values, said circuit arrangement comprising: separating means having an input receiving said train of two-bit words and first and second outputs, said first output generating a first stream of said first bits in serialized form from said train of two-bit words, said second output generating a second stream of said second bits in serialized form corresponding to said train of two-bit words; first detecting means connected to said first output and responsive to the appearance of consecutive first bits of one of said binary values for generating an output representing an error count; second means connected with said second output and responsive to consecutive second bits of the other of said binary values for generating an output representing an error count; and counting means connected to outputs of said first and second means for totaling said counts representing said errors.
Claim 3
Dependent Claim
93 words
The circuit arrangement defined in claim 1 wherein said separating means includes a timing pulse extraction unit outputting a clock signal of a frequency which is half of the frequency of said line code; and first and second D-type bistable circuits having data inputs connected to a transmission line carrying said line code and timing inputs connected to said timing pulse extraction unit for receiving respectively said clock pulse and an inverted clock pulse train, each of said bistable circuits being formed with a respective one of said outputs of said separating means.
Claim 4
Dependent Claim
50 words
The circuit arrangement defined in claim 2 wherein said first detecting means includes a third D-type bistable circuit having a data input receiving said clock pulses from said timing pulse extraction unit; and a NOR-type logic circuit having a first input receiving an inverted output of said first bistable circuit.
Claim 5
Dependent Claim
71 words
The circuit arrangement defined in claim 3 wherein said detecting means includes: a fourth D-type bistable circuit having a data input connected to said second output and a timing input receiving said inverted clock pulse from said timing pulse extraction unit; and a second NOR-type logic circuit having a first input receiving an output from said second bistable circuit and a second input receiving an output from said fourth bistable circuit.
Claim 6
Dependent Claim
74 words
The circuit arrangement defined in claim 4 wherein said counting means includes: an OR-type logic circuit having inputs connected to said outputs with said first and second means; and a fifth D-type bistable circuit having a data input connected to an output of said OR-type logic circuit and a timing input receiving said inverted clock pulse from said timing pulse extraction unit, a counter being connected to the output of said fifth bistable circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-13 | 1990-10-13 | 1991-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-13 | 1994-10-13 | 1995-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-13 | 1998-10-13 | 1999-04-14 | $7700.00 | Window Closed / Lapsed |