Patent US4658378A successfully refreshed from Google Patents.
US4658378A
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Polysilicon resistor with low thermal activation energy
Assignee: Inmos Corp
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Filing: 1982-12-15
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Granted: 1987-04-14
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Expires: 2002-12-15
Abstract
Abstract An improved load resistor for a VLSI memory cell is formed in polysilicon by having P-type (such as boron) impurities in a middle region and n-type (such as phosphorous or arsenic) impurities on the sides, with the concentrations being in a range so that the thermal activation energy is below about 0.5 eV. Further, the middle region can be doped additionally with arsenic or phosphorous in an amount equal to or less than the boron. This gives good leakage current masking over a range of -55° to +125° C. without drawing excessive current, and is less sensitive to impurities.
Inventors
- 👤 Ronald R. Bourassa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:57
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
139 words
A method of using a polysilicon structure as a resistance device in a semiconductor circuit comprising the steps of: coupling a polysilicon structure in circuit with portions of an integrated circuit, applying a voltage across said polysilicon structure, and obtaining a current through said polysilicon structure proportional to said voltage, said polysilicon structure comprising a polysilicon region, a selected one of N-type and P-type impurities defining a middle area in said polysilicon region, the other one of said N-type and N-type impurities defining other areas located in said polysilicon region on the sides of said middle area, a PN junction being defined on one side of said middle area and an NP junction being defined at the other side of said middle area, the concentration of impurities in said middle area being greater than 10 18 per cubic centimeter.
Claim 2
Independent Claim
139 words
A method of using a polysilicon structure as a resistance device in a semiconductor circuit comprising the steps of: coupling a polysilicon structure in circuit with portions of an integrated circuit, applying a voltage across said polysilicon structure, and obtaining a current through said polysilicon structure proportional to said voltage, said polysilicon structure comprising a polysilicon region, a selected one of N-type and P-type impurities defining a middle area in said polysilicon region, the other one of said N-type and N-type impurities defining other areas located in said polysilicon region on the sides of said middle area, a PN junction being defined on one side of said middle area and an NP junction being defined at the other side of said middle area, the concentration of impurities in said middle area being greater than 10 18 per cubic centimeter.
Claim 3
Dependent Claim
41 words
The method according to claim 1 wherein said side areas contain concentrations of impurities of between 10 18 and 10 21 , and wherein said concentration of said middle area is lower than the concentration of impurities in said side areas.
Claim 4
Dependent Claim
25 words
The method according to claim 1 wherein said middle area is doped with boron and said side areas are doped with an N type impurity.
Claim 5
Dependent Claim
21 words
The method according to claim 1 wherein said middle area includes both an N type impurity and a P type impurity.
Claim 6
Dependent Claim
35 words
The method according to claim 4 wherein the concentration of said P type impurity in said middle area is equal to or greater than said concentration of said N type impurity in said middle area.
Claim 7
Dependent Claim
80 words
The method according to claim 1 wherein said middle area is doped with a P type impurity to a concentration greater than 10 18 per cubic centimeter, said side regions are doped with an N type impurity to a concentration of between 10 18 and 10 20 per cubic centimeter, said middle area contacting said two side areas and defining an electrical path therethrough, the contact of said middle area to said two side areas forming a pair of junctions.
Claim 8
Dependent Claim
75 words
The method of claim 1 wherein said semiconductor circuit comprises a static RAM of the type having memory cells each including a flip-flop with load resistances, said polysilicon structure operating as a said load resistance, said method including operating said static RAM by storing data in a memory cell thereof, said step of applying a voltage comprising passing current through said polysilicon structure from a source of operating voltage to a node within said flip-flop.
Claim 9
Dependent Claim
38 words
The method according to claim 7 wherein said resistance is between about 0.1 and about 50 gigaohms when said voltage is five volts over a temperature range of about minus 55 degrees centigrade to plus 125 degrees centigrade.
Claim 10
Independent Claim
184 words
A method of using polysilicon structures as a load resistance in a semiconductor static RAM of the type including plural memory cells each having a pair of cross-coupled transistors, each of said transistors having gate electrodes, comprising: coupling a pair of polysilicon structures between said gate electrodes and a source of operating voltage, and storing data in said memory cells by causing said cross-coupled transistors to assume a state corresponding to said data, thereby obtaining currents through said polysilicon structures proportional to the voltages across them, said polysilicon structures operating as load resistors, each of said polysilicon structures comprising a polysilicon region, a selected one of N-type and P-type impurities defining a middle area in said polysilicon region, the other one of said N-type and P-type impurities defining other areas located in said polysilicon region on the sides of said middle area, a PN junction being defined on one side of said middle area and an NP junction being defined at the other side of said middle area, the concentration of impurities in said middle area being greater than 10 18 per cubic centimeter.
Claim 11
Independent Claim
184 words
A method of using polysilicon structures as a load resistance in a semiconductor static RAM of the type including plural memory cells each having a pair of cross-coupled transistors, each of said transistors having gate electrodes, comprising: coupling a pair of polysilicon structures between said gate electrodes and a source of operating voltage, and storing data in said memory cells by causing said cross-coupled transistors to assume a state corresponding to said data, thereby obtaining currents through said polysilicon structures proportional to the voltages across them, said polysilicon structures operating as load resistors, each of said polysilicon structures comprising a polysilicon region, a selected one of N-type and P-type impurities defining a middle area in said polysilicon region, the other one of said N-type and P-type impurities defining other areas located in said polysilicon region on the sides of said middle area, a PN junction being defined on one side of said middle area and an NP junction being defined at the other side of said middle area, the concentration of impurities in said middle area being greater than 10 18 per cubic centimeter.
Claim 12
Dependent Claim
41 words
The method according to claim 9 wherein said side areas contain concentrations of impurities of between 10 18 and 10 21 , and wherein said concentration of said middle area is lower than the concentration of impurities in said side areas.
Claim 13
Dependent Claim
25 words
The method according to claim 10 wherein said middle area is doped with boron and said side areas are doped with an N type impurity.
Claim 14
Dependent Claim
21 words
The method according to claim 10 wherein said middle area includes both an N type impurity and a P type impurity.
Claim 15
Dependent Claim
35 words
The method according to claim 12 wherein the concentration of said P type impurity in said middle area is equal to or greater than said concentration of said N type impurity in said middle area.
Claim 16
Dependent Claim
80 words
The method according to claim 9 wherein said middle area is doped with a P type impurity to a concentration greater than 10 18 per cubic centimeter, said side regions are doped with an N type impurity to a concentration of between 10 18 and 10 20 per cubic centimeter, said middle area contacting said two side areas and defining an electrical path therethrough, the contact of said middle area to said two side areas forming a pair of junctions.
Claim 17
Dependent Claim
38 words
The method according to claim 10 wherein said resistance is between about 0.1 and about 50 gigaohms when said voltage is five volts over a temperature range of about minus 55 degrees centigrade to plus 125 degrees centigrade.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-13 | 1990-10-13 | 1991-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-13 | 1994-10-13 | 1995-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-13 | 1998-10-13 | 1999-04-14 | $7700.00 | Window Closed / Lapsed |