Patent US4656368A successfully refreshed from Google Patents.
US4656368A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed master-slave flip-flop
Assignee: MagnaChip Semiconductor Ltd
•
Filing: 1985-09-13
•
Granted: 1987-04-07
•
Expires: 2005-09-13
Abstract
Abstract A flip-flop including a master section having an input for receiving a data signal and a pair of outputs, one output for providing the data signal state, and one output for providing the data signal state complement, and a slave section having a pair of inputs, one connected to each of the outputs of the master section, and a pair of outputs, one of the outputs of the slave section for providing the data signal state, and one of the outputs of the slave section for providing the data signal state complement. A cross coupling circuit is provided in the slave section for connecting the slave section input for receiving the data signal state to the slave section output for providing the data signal state, and for connecting the slave section input for receiving the data signal state complement to the slave section output for providing the data signal state complement. Pass means are provided in the cross coupling circuit for controlling coupling between the slave section outputs and the slave section inputs, and a clock is provided for controlling the master section and the pass means such that the pass means decouples the cross coupling circuit when the data state and data state complement are provided by the master section outputs to the slave section inputs.
Inventors
- 👤 Craig C. McCombs
- 👤 Richard D. Farris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:13
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372; H03K3/353; H03K3/356; H03K3/3562
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
425 words
A flip-flop comprising: clock means having an input for receiving a clock signal, a clock output having a high state when the clock signal is high and a low state when the clock signal is low, and an inverted clock output having a low state when the clock signal is high and a high state when the clock signal is low; a master section having a data input for receiving a data signal, a latching means connected to said clock means for latching the state of the data signal, a master output for providing the state latched by said latching means and an inverted master output for providing the complement of the state latched by said latching means, said latching means comprises a first master section inverter having an input connected to the data input of said master section and an output connected to said inverted master output, a second master section inverter having an input connected to the output of said first master section inverter and an output connected to the input of said first master section inverter and the master output, and a pass transistor connected between the output of said second master section inverter and the input of said first master section inverter and controlled by the state on said inverted clock output for turning off when the state is low and turning on when the state on the inverted clock output is high; a slave section having a first slave input connected to said master output, a second inverted slave input connected to said inverted master output, a slave output for providing the state of the latched data signal, and an inverted slave output for providing the inverted state of the latched data signal; cross coupling means in said slave section and controlled by said clock output such that said slave output is connected to said first slave input and said second inverted slave output is connected to said inverted slave input when the state of said clock output is high, and said slave output and said inverted slave output are not connected to said first slave input and said second inverted slave input when said clock signal is low; and isolation means between said master section and said slave section and controlled by said inverted clock output such that said master section is disconnected from said slave section when there is a low state on said inverted clock output, and said master section is connected to said slave section when there is a high state on said inverted clock output.
Claim 2
Dependent Claim
425 words
A flip-flop comprising: clock means having an input for receiving a clock signal, a clock output having a high state when the clock signal is high and a low state when the clock signal is low, and an inverted clock output having a low state when the clock signal is high and a high state when the clock signal is low; a master section having a data input for receiving a data signal, a latching means connected to said clock means for latching the state of the data signal, a master output for providing the state latched by said latching means and an inverted master output for providing the complement of the state latched by said latching means, said latching means comprises a first master section inverter having an input connected to the data input of said master section and an output connected to said inverted master output, a second master section inverter having an input connected to the output of said first master section inverter and an output connected to the input of said first master section inverter and the master output, and a pass transistor connected between the output of said second master section inverter and the input of said first master section inverter and controlled by the state on said inverted clock output for turning off when the state is low and turning on when the state on the inverted clock output is high; a slave section having a first slave input connected to said master output, a second inverted slave input connected to said inverted master output, a slave output for providing the state of the latched data signal, and an inverted slave output for providing the inverted state of the latched data signal; cross coupling means in said slave section and controlled by said clock output such that said slave output is connected to said first slave input and said second inverted slave output is connected to said inverted slave input when the state of said clock output is high, and said slave output and said inverted slave output are not connected to said first slave input and said second inverted slave input when said clock signal is low; and isolation means between said master section and said slave section and controlled by said inverted clock output such that said master section is disconnected from said slave section when there is a low state on said inverted clock output, and said master section is connected to said slave section when there is a high state on said inverted clock output.
Claim 3
Dependent Claim
70 words
The flip-flop of claim 1 further comprising a data pass transistor between the data input of the master section and the input of said first master section inverter, said data pass transistor controlled by the state on said clock output such that said data pass transistor is turned on when the state on said clock output is high and turned off when the state on said clock output is low.
Claim 4
Dependent Claim
41 words
The flip-flop of claim 2 wherein said slave section includes a first slave section inverter between said first slave input and said inverted slave output, and a second slave section inverter between said second inverted slave input and said slave output.
Claim 5
Dependent Claim
69 words
The flip-flop of claim 3 further comprising a reset input for receiving a reset signal; and wherein said second master section inverter and said second slave section inverter are both NOR gates, each of said NOR gates having an input connected to said reset input for resetting said slave output and said inverted slave output to a desired state upon receipt of a reset signal on said reset input.
References Cited (Backward Citations)
US3609569A
Cited
US4181862A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-06 | 1990-10-06 | 1991-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-06 | 1994-10-06 | 1995-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-06 | 1998-10-06 | 1999-04-07 | $7700.00 | Window Closed / Lapsed |