Patent US839516A successfully refreshed from Google Patents.
Patent FR577204A successfully refreshed from Google Patents.
US4654584A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed precision equivalent time sampling A/D converter and method
Assignee: Analogic Corp
•
Filing: 1985-12-12
•
Granted: 1987-03-31
•
Expires: 2005-12-12
Abstract
Abstract A circuit for precisely measuring very high-speed recurring waveforms includes a comparator coupled between an analog input terminal and a successive approximation register. A digital-to-analog converter is also coupled between the digital output circuit of the successive approximation register and the second input terminal of the comparator, and a high-speed digital latch is coupled between the output of the comparator and the input of the successive approximation register for freezing the output states of the comparator upon the application of hold signals from a hold signal generator means, so that a first sequential series of hold signals are applied to the latch, coincident in time with the occurrence of a first portion of the recurring analog waveforms being measured, until the successive approximation register completes its measurement of the voltage amplitude of such first portion. A counter in the hold signal generator means is thereafter stepped, to enable the measurement of a second portion of the recurring waveform, adjacent the first portion, to be carried out by the application of a second series of hold signals, each coincident in time with the occurrence of the second portion of the waveform, until the voltage amplitude at the second portion is evaluated by the iterative operation of the successive approximation register. The counter is again stepped, and the process is repeated until numerous points upon the recurring waveform under examination are measured.
Inventors
- 👤 Colin Gyles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:46
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/20; G01R13/22; G01R13/34; G01R13/345; H; H03; H03M; H03M1/00; H03M1/12; H03M1/124; H03M1/1245; H03M1/1285; H03M1/34; H03M1/38; H03M1/46
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
289 words
A circuit for precisely measuring high speed analog input signals that repeat during time periods under examination comprising: successive approximation register means having an input and output circuit; comparator means having an output circuit, a first input circuit for receiving said high-speed analog signals and a second input circuit; a digital-to-analog converter means, coupled between the digital output circuit of said successive approximation register means and the second input circuit of said comparator and having a given settling time; high-speed latch means coupled between the output circuit of said comparator and the input circuit of said successive approximation register means for freezing the output state of said comparator upon the application of a hold signal to the hold terminal of said latch means; and hold signal generator means for (a) applying a first sequential series of hold signals to the hold terminal of said latch means, each being coincident in time with the occurrence of a first portion of said analog signals, until said successive approximation register means completes its measurement of the amplitude of said first portion, said hold signals being separated from each other for a time equal to or greater than the settling time of said converter; (b) thereafter applying a second sequential series of hold signals to the hold terminal of said latch means, each being coincident in time with the occurrence of a second portion of said signals different from said first portion, until said successive approximation register means completes its measurement of the amplitude of said second portion, said hold signals being separated from each other for a time equal to or greater than the settling time of said converter, and so on until all desired portions of said analog signals are measured.
Claim 2
Dependent Claim
289 words
A circuit for precisely measuring high speed analog input signals that repeat during time periods under examination comprising: successive approximation register means having an input and output circuit; comparator means having an output circuit, a first input circuit for receiving said high-speed analog signals and a second input circuit; a digital-to-analog converter means, coupled between the digital output circuit of said successive approximation register means and the second input circuit of said comparator and having a given settling time; high-speed latch means coupled between the output circuit of said comparator and the input circuit of said successive approximation register means for freezing the output state of said comparator upon the application of a hold signal to the hold terminal of said latch means; and hold signal generator means for (a) applying a first sequential series of hold signals to the hold terminal of said latch means, each being coincident in time with the occurrence of a first portion of said analog signals, until said successive approximation register means completes its measurement of the amplitude of said first portion, said hold signals being separated from each other for a time equal to or greater than the settling time of said converter; (b) thereafter applying a second sequential series of hold signals to the hold terminal of said latch means, each being coincident in time with the occurrence of a second portion of said signals different from said first portion, until said successive approximation register means completes its measurement of the amplitude of said second portion, said hold signals being separated from each other for a time equal to or greater than the settling time of said converter, and so on until all desired portions of said analog signals are measured.
Claim 3
Dependent Claim
32 words
The combination as set forth in claim 1 including means for operating said hold signal generator means in response to repetitive trigger events associated with particular portions of said high-speed analog signals.
Claim 4
Dependent Claim
72 words
The combination as set forth in claim 2 wherein said hold signal generator means comprises an equivalent time sampler without a track-and-hold circuit and analog-to-digital converter, for generating groups of hold signals applied to said latch means, each group of hold signals having delays relative to the times of occurrences of said trigger events differing from the delays of other groups to enable the reconstruction of the waveform of said analog signals.
Claim 5
Dependent Claim
61 words
The combination as set forth in claim 3 wherein said hold signal generator means includes counter means coupled to the output circuit of said successive approximation register means for altering said delays to enable reconstruction of said waveforms, and means for stepping said counter means upon the completion of the measurement of each waveform portion by said successive approximation register means.
Claim 6
Dependent Claim
23 words
The combination as set forth in claim 4 including means for reading out the count within said counter to provide digital time data.
Claim 7
Dependent Claim
28 words
The combination as set forth in claim 1 wherein said comparator means and said latch means are contained within a test probe for receiving said analog input signals.
Claim 8
Dependent Claim
28 words
The combination as set forth in claim 2 wherein said comparator means and said latch means are contained within a test probe for receiving said analog input signals.
Claim 9
Dependent Claim
28 words
The combination as set forth in claim 3 wherein said comparator means and said latch means are contained within a test probe for receiving said analog input signals.
Claim 10
Dependent Claim
28 words
The combination as set forth in claim 4 wherein said comparator means and said latch means are contained within a test probe for receiving said analog input signals.
Claim 11
Dependent Claim
28 words
The combination as set forth in claim 5 wherein said comparator means and said latch means are contained within a test probe for receiving said analog input signals.
Claim 12
Dependent Claim
22 words
The combination as set forth in claim 1 including a digital output bus coupled to the output of said successive approximation register.
Claim 13
Dependent Claim
23 words
The combination as set forth in claim 1 including an analog data output lead coupled to the output of said digital-to-analog converter means.
Claim 14
Dependent Claim
112 words
Method of precisely measuring a single high speed analog input waveform that repeats during time periods under examination, comprising the steps of: (a) partially measuring the amplitude of a first particular portion of said waveform a plurality of times during a first repetitive series of examination intervals, until an accurate final measurement of the amplitude of said first particular portion is obtained; (b) repeating step (a) for a number of subsequent repetitive series of examination intervals, while measuring a given particular portion of said waveform during each series of examination intervals, each given particular portion differing from the particular portions examined during other series of examination intervals, thereby to measure said waveform.
Claim 15
Dependent Claim
112 words
Method of precisely measuring a single high speed analog input waveform that repeats during time periods under examination, comprising the steps of: (a) partially measuring the amplitude of a first particular portion of said waveform a plurality of times during a first repetitive series of examination intervals, until an accurate final measurement of the amplitude of said first particular portion is obtained; (b) repeating step (a) for a number of subsequent repetitive series of examination intervals, while measuring a given particular portion of said waveform during each series of examination intervals, each given particular portion differing from the particular portions examined during other series of examination intervals, thereby to measure said waveform.
Claim 16
Dependent Claim
44 words
The method of claim 13 wherein said waveform is measured after given delays following the occurrence of a trigger event, said delays being different for each series of examination intervals, each trigger event being correlated in time with a particular portion of said waveform.
References Cited (Backward Citations)
US3456189A
Cited
US3484591A
Cited
US3662380A
Cited
US4047115A
Cited
US4353057A
Cited
US4225940A
Cited
US4283713A
Cited
US4345241A
Cited
US4362394A
Cited
US4507740A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |