MOS amplifier and semiconductor memory using the same

Claim 2

An MOS amplifier comprising: first and second insulated gate field effect transistors respectively coupled to one another for differentially amplifying input signals applied to the gates of said first and second insulated gate field effect transistors; a third insulated gate field effect transistor receiving at the drain thereof a current corresponding to the drain current of said first insulated gate field effect transistor; a fourth insulated gate field effect transistor receiving at the drain thereof a current corresponding to the drain current of said second insulated gate field effect transistor; a positive feedback circuit applying the drain potential of said third insulated gate field effect transistor to the gate of said fourth insulated gate field effect transistor, and the drain potential of said fourth insulated gate field effect transistor to the gate of said third insulated gate field effect transistor; a first output node whose level is determined by the drain potential of said third insulated gate field effect transistor; a second output node whose level is determined by the drain potential of said fourth insulated gate field effect transistor; a first current mirror circuit receiving the drain current of said first insulated gate field effect transistor, and producing a current to be supplied to the drain of said third insulated gate field effect transistor; and a second current mirror circuit receiving the drain current of said second insulated gate field effect transistor and producing a current to be supplied to the drain of said fourth insulated gate field effect transistor.

Claim 3

An MOS amplifier according to claim 1, wherein the gate of said first insulated gate field effect transistor is coupled to receive an input signal which is complementary to an input signal applied to the gate of said second insulated gate field effect transistor.

Claim 4

An MOS amplifier according to claim 1, wherein a signal to be amplified is applied to the gate of said first insulated gate field effect transistor and a reference signal having a predetermined reference level is applied to the gate of said second insulated gate field effect transistor.

Claim 5

An MOS amplifier according to claim 1, wherein each of said first and second current mirror circuits are comprised of insulated gate field effect transistors of a first channel conductivity type, and each of said first through fourth insulated gate field effect transistors are comprised of an insulated gate field effect transistor of a second channel conductivity type opposite to said first channel conductivity type.

Claim 6

An MOS amplifier according to claim 4, which further includes a fifth insulated gate field effect transistor of said second channel conductivity type, and in which the sources of said first through fourth insulated gate field effect transistors are connected in common, and said fifth insulated gate field effect transistor is disposed between the sources thus connected in common and a reference potential point of the circuit.

Claim 7

An MOS amplifier according to claim 5, wherein a gate of said fifth insulated gate field effect transistor is coupled to receive a timing signal which controls the conduction of said fifth insulated gate field effect transistor to render the amplifier operative when said timing signal has a first level of voltage and inoperative when said timing signal has a second level of voltage.

Claim 8

An MOS amplifier according to claim 6, wherein the gate of said first insulated gate field effect transistor is coupled to receive an input signal which is complementary to an input signal applied to the gate of said second insulated gate field effect transistor.

Claim 9

A semiconductor memory comprising: a memory matrix comprised of a plurality of data lines, a plurality of word lines, and a plurality of memory cells having data input-output terminals connected to corresponding data lines, and selection terminals connected to corresponding word lines, respectively; a pair of common data lines; a column switch circuit receiving a selection signal and including means for connecting a pair of data lines designated by the selection signal from a plurality of said data lines to the pair of common data lines; and an amplifier having a pair of input terminals connected to the pair of said common data lines; said amplifier comprising: a pair of first and second insulated gate field effect transistors receiving at the gates thereof a potential difference between said common data lines; a third insulated gate field effect transistor receiving at the drain thereof a current corresponding to the drain current of said first insulated gate field effect transistor; a fourth insulated gate field effect transistor receiving at the drain thereof a current corresponding to the drain current of said second insulated gate field effect transistor; a feedback circuit applying the drain potential of said third insulated gate field effect transistor to the gate of said fourth insulated gate field effect transistor, and applying the drain potential of said fourth insulated gate field effect transistor to the gate of said third insulated gate field effect transistor; a first output node whose level is determined by the drain potential of said third insulated gate field effect transistor; and a second output node whose level is determined by the drain potential of said fourth insulated gate field effect transistor.

Claim 10

A semiconductor memory comprising: a memory matrix comprised of a plurality of data lines, a plurality of word lines, and a plurality of memory cells having data input-output terminals connected to corresponding data lines, and selection terminals connected to corresponding word lines, respectively; a pair of common data lines; a column switch circuit receiving a selection signal and including means for connecting a pair of data lines designated by the selection signal from a plurality of said data lines to the pair of common data lines; and an amplifier having a pair of input terminals connected to the pair of said common data lines; said amplifier comprising: a pair of first and second insulated gate field effect transistors receiving at the gates thereof a potential difference between said common data lines; a third insulated gate field effect transistor receiving at the drain thereof a current corresponding to the drain current of said first insulated gate field effect transistor; a fourth insulated gate field effect transistor receiving at the drain thereof a current corresponding to the drain current of said second insulated gate field effect transistor; a feedback circuit applying the drain potential of said third insulated gate field effect transistor to the gate of said fourth insulated gate field effect transistor, and applying the drain potential of said fourth insulated gate field effect transistor to the gate of said third insulated gate field effect transistor; a first output node whose level is determined by the drain potential of said third insulated gate field effect transistor; and a second output node whose level is determined by the drain potential of said fourth insulated gate field effect transistor.

Claim 11

A semiconductor memory according to claim 8, wherein said amplifier further includes a fifth insulated gate field effect transistor and which the sources of said first through fourth insulated gate field effect transistors are connected in common, and said fifth insulated gate field effect transistor is disposed between the sources thus connected in common and a reference potential point of the circuit.

Claim 12

A semiconductor memory according to claim 8, wherein said pair of common data lines provide data signals that are complementary to one another, respectively, and wherein said first insulated gate field effect transistor has its gate coupled to one of said pair of common data lines and the second insulated gate field effect has its gate coupled to the other of said pair of common data lines so that said first and second insulated gate field effect transistors receive complementary data signals.

Claim 13

A semiconductor memory according to claim 10, which further includes: a first current mirror circuit receiving the drain current of said first insulated gate field effect transistor, and producing a current to be supplied to the drain of said third insulated gate field effect transistor; and a second current mirror cirucit receiving the drain current of said second insulated gate field effect transistor and producing a current to be supplied to the drain of said fourth insulated gate field effect transistor.

Claim 14

A semiconductor memory according to claim 11, wherein each of said first and second current mirror circuits are comprised of insulated gate field effect transistors of a first channel conductivity type, and each of said first through fourth insulated gate field effect transistors are comprised of an insulated gate field effect transistor of a second channel conductivity type opposite to said first channel conductivity type.

Claim 15

A semiconductor memory according to claim 12, which further includes a fifth insulated gate field effect transistor of said second channel conductivity type, and in which the sources of said first through fourth insulated gate field effect transistors are connected in common, and said fifth insulated gate field effect transistor is disposed between the sources thus connected in common and a reference potential point of the circuit.

Claim 16

A semiconductor memory according to claim 13, wherein a gate of said fifth insulated gate field effect transistor is coupled to receive a timing signal which controls the conduction of said fifth insulated gate field effect transistor to render the amplifier operative when said timing signal has a first level of voltage and inoperative when said timing signal has a second level of voltage.

Claim 17

An MOS amplifier comprising: first and second insulated gate field effect transistors respectively coupled to one another for differentially amplifying input signals applied to the gates of said first and second insulated gate field effect transistors, wherein the source of said first and second insulated gate field effect transistors are coupled in common to one another; a third insulated gate field effect transistor having its source-drain path coupled in series with the source-drain path of said first insulated gate field effect transistor, said third insulated gate field effect transistor being located between a first reference voltage source and said first insulated gate field effect transistor so that the drain of said third insulated gate field effect transistor is coupled to the drain of said first insulated gate field effect transistor; a fourth insulated gate field effect transistor having its source-drain path coupled in series with the source-drain path of said second insulated gate field effect transistor, said fourth insulated gate field effect transistor being located between the first reference voltage source and said second insulated gate field effect transistor so that the drain of said fourth insulated gate field effect transistor is coupled to the drain of said second insulated gate field effect transistor; a positive feedback circuit applying the drain potential of said third insulated gate field effect transistor to the gate of said fourth insulated gate field effect transistor, and the drain potential of the fourth insulated gate field effect transistor to the gate of said third insulated gate field effect transistor; a first output node coupled between the drains of said first and third insulated gate field effect transistors; a second output node coupled between the drains of said second and fourth insulated gate field effect transistor; a fifth insulated gate field effect transistor coupled between the common sources of said first and second insulated gate field effect transistors and a second reference potential, wherein a gate of said fifth insulated gate field effect transistor is coupled to receive a timing signal which controls the conduction of said fifth insulated gate field effect transistor to render the amplifier operative when said timing signal has a first level of voltage and inoperative when said timing signal has a second level of voltage; and a sixth insulated gate field effect transistor coupled in parallel with said third insulated gate field effect transistor between said first reference potential and said first output node and a seventh insulated gate field effect transistor coupled in parallel with said fourth insulated gate field effect transistor between said first reference potential and said second output node, wherein gates of said sixth and seventh insulated gate field effect transistors are coupled to receive the same timing signal which is applied to the gate of said fifth insulated gate field effect transistor, and wherein said sixth and seventh insulated gate field effect transistors have a conductivity type opposite to that of said fifth insulated gate field effect transistor so that when said timing signal has said second voltage level rendering said amplifier inoperative, said sixth and seventh insulated gate field effect transistors will be turned on to reset said first and second output nodes to a level substantially corresponding to that of said first reference voltage source.

Claim 18

An MOS amplifier comprising: first and second insulated gate field effect transistors respectively coupled to one another for differentially amplifying input signals applied to the gates of said first and second insulated gate field effect transistors, wherein the source of said first and second insulated gate field effect transistors are coupled in common to one another; a third insulated gate field effect transistor having its source-drain path coupled in series with the source-drain path of said first insulated gate field effect transistor, said third insulated gate field effect transistor being located between a first reference voltage source and said first insulated gate field effect transistor so that the drain of said third insulated gate field effect transistor is coupled to the drain of said first insulated gate field effect transistor; a fourth insulated gate field effect transistor having its source-drain path coupled in series with the source-drain path of said second insulated gate field effect transistor, said fourth insulated gate field effect transistor being located between the first reference voltage source and said second insulated gate field effect transistor so that the drain of said fourth insulated gate field effect transistor is coupled to the drain of said second insulated gate field effect transistor; a positive feedback circuit applying the drain potential of said third insulated gate field effect transistor to the gate of said fourth insulated gate field effect transistor, and the drain potential of the fourth insulated gate field effect transistor to the gate of said third insulated gate field effect transistor; a first output node coupled between the drains of said first and third insulated gate field effect transistors; a second output node coupled between the drains of said second and fourth insulated gate field effect transistor; a fifth insulated gate field effect transistor coupled between the common sources of said first and second insulated gate field effect transistors and a second reference potential, wherein a gate of said fifth insulated gate field effect transistor is coupled to receive a timing signal which controls the conduction of said fifth insulated gate field effect transistor to render the amplifier operative when said timing signal has a first level of voltage and inoperative when said timing signal has a second level of voltage; and a sixth insulated gate field effect transistor coupled in parallel with said third insulated gate field effect transistor between said first reference potential and said first output node and a seventh insulated gate field effect transistor coupled in parallel with said fourth insulated gate field effect transistor between said first reference potential and said second output node, wherein gates of said sixth and seventh insulated gate field effect transistors are coupled to receive the same timing signal which is applied to the gate of said fifth insulated gate field effect transistor, and wherein said sixth and seventh insulated gate field effect transistors have a conductivity type opposite to that of said fifth insulated gate field effect transistor so that when said timing signal has said second voltage level rendering said amplifier inoperative, said sixth and seventh insulated gate field effect transistors will be turned on to reset said first and second output nodes to a level substantially corresponding to that of said first reference voltage source.