Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a semiconductor substrate of a first type of conductivity; a gate electrode formed over said semiconductor substrate; two semiconductor regions of a second type of conductivity formed in said semiconductor substrate on both sides of said gate electrode, said two semiconductor regions serving as a source region and a drain region, respectively; means for applying voltages to said gate electrode and to said two semiconductor regions; and means for establishing a predetermined large potential difference in said source region with respect to said gate electrode so that carriers are injected into said gate electrode from said source region due to said large potential difference with respect to said gate electrode.

Claim 3

A semiconductor memory device according to claim 1, wherein said gate electrode comprises a first gate electrode and a second gate electrode formed over said first gate electrode, and wherein said carriers are injected into said first gate electrode, and a voltage is applied to said second gate electrode from said voltage-applying means.

Claim 4

A semiconductor memory device comprising: a semiconductor substrate of a first type of conductivity; a first gate electrode formed on a first insulating film on said semiconductor substrate; a second gate electrode formed on a second insulating film on said first gate electrode; and a source region and a drain region of a second type of conductivity, that are formed in said semiconductor substrate on both sides of said first and second gate electrodes, at least said source region being comprised of a first portion that is adjacent to said gate electrodes and that has a low impurity concentration, and a second portion that is remote from said gate electrodes and that has a high impurity concentration; wherein carriers are injected into said first electrode from the first portion of said source region.

Claim 5

A semiconductor memory device comprising: a semiconductor substrate of a first type of conductivity; a first gate electrode formed on a first insulating film on said semiconductor substrate; a second gate electrode formed on a second insulating film on said first gate electrode; and a source region and a drain region of a second type of conductivity, that are formed in said semiconductor substrate on both sides of said first and second gate electrodes, at least said source region being comprised of a first portion that is adjacent to said gate electrodes and that has a low impurity concentration, and a second portion that is remote from said gate electrodes and that has a high impurity concentration; wherein carriers are injected into said first electrode from the first portion of said source region.

Claim 6

A semiconductor memory device according to claim 3, wherein the impurity concentration in said first portion ranges from 1×10 16 to 1×10 17 atoms/cm 3 .

Claim 7

A semiconductor memory device according to claim 4, wherein the impurity concentration in said second portion ranges from 1×10 20 to 1×10 21 atoms/cm 3 .

Claim 8

A semiconductor memory device according to claim 3, wherein said first and second types of conductivities are the p-type and the n-type, respectively.

Claim 9

A semiconductor memory device according to claim 3, wherein said first portion is formed in said source region only.

Claim 10

A semiconductor memory device according to claim 7, wherein said second portion of said source region has the same impurity concentration as that of said drain region.

Claim 11

A semiconductor memory device according to claim 3, further comprising an insulating film formed on at least one of the two side walls of said gate electrodes, wherein said first portion of said source region is formed using said gate electrodes as a mask, and said second portion of said source region is formed using said gate electrodes and the insulating film on the side wall as a mask.

Claim 12

A semiconductor memory device according to claim 9, wherein said first portion is shallower than said second portion.

Claim 13

A semiconductor memory device according to claim 9, wherein said first portion is formed in said source region only.

Claim 14

A semiconductor memory device according to claim 11, wherein the insulating film of said side wall is formed only on the source side of said gate electrodes.

Claim 15

A semiconductor memory device according to claim 3, wherein a portion of said first insulating film on the source side is thinner than the other thereof.

Claim 16

A semiconductor memory device according to claim 1, wherein said source region is not overlapped by any gate electrode.

Claim 17

A semiconductor memory device according to claim 3, wherein the first portion of said source region is not overlapped by any gate electrode.

Claim 18

A semiconductor memory device comprising: a semiconductor substrate of a first type of conductivity; word lines formed in rows over said semiconductor substrate; data lines formed in columns over said semiconductor substrate; memory cells provided at intersecting points of said word lines and said data lines, each of said memory cells being comprised of a floating gate electrode formed on said semiconductor substrate, a control gate electrode formed on said floating gate electrode, and a source region and a drain region of a second type of conductivity that are formed in said semiconductor substrate on both sides of the gate electrodes, said control gate electrode and said drain region being connected to said word line and said data line, respectively; wherein at least said source region is comprised of a first portion that is adjacent to said gate electrodes and that has a low impurity concentration, and a second portion that is remote from said gate electrodes and that has a high impurity concentration, and wherein carriers are injected into said floating gate electrode from said first portion of said source region.

Claim 19

A semiconductor memory device comprising: a semiconductor substrate of a first type of conductivity; word lines formed in rows over said semiconductor substrate; data lines formed in columns over said semiconductor substrate; memory cells provided at intersecting points of said word lines and said data lines, each of said memory cells being comprised of a floating gate electrode formed on said semiconductor substrate, a control gate electrode formed on said floating gate electrode, and a source region and a drain region of a second type of conductivity that are formed in said semiconductor substrate on both sides of the gate electrodes, said control gate electrode and said drain region being connected to said word line and said data line, respectively; wherein at least said source region is comprised of a first portion that is adjacent to said gate electrodes and that has a low impurity concentration, and a second portion that is remote from said gate electrodes and that has a high impurity concentration, and wherein carriers are injected into said floating gate electrode from said first portion of said source region.

Claim 20

A semiconductor memory device according to claim 16, wherein said source region only has said first and second portions.

Claim 21

A semiconductor memory device according to claim 17, further comprising an insulating film formed on the side wall on the source side of said gate electrodes, wherein said first portion of said source region is formed using said gate electrodes as a mask, and said second portion of said source region is formed using said gate electrodes and the insulating film on the side wall as a mask.

Claim 22

A semiconductor memory device according to claim 16, wherein the first portion of said source region is not overlapped by any gate electrode.