Two-input crosstalk-resistant adaptive noise canceller

Claim 2

An adaptive noise canceller, comprising: first means for receiving a primary signal having a first desired portion and a second undesired noise portion; second means for receiving, during each of a successive sequence of time intervals (n); a reference signal (r(n)) having a first crosstalk portion with a time-amplitude characteristic similar to that of said primary signal first portion and a second noise portion with a time-amplitude characteristic similar to that of said primary signal second portion; first summer means for subtracting from said primary signal, received from said first means, a noise reference signal (w(n)) to provide an output signal (S(n)) having said primary signal first portion and a second undesirable noise portion which is of reduced amplitude with respect to the amplitude of the primary signal second portion; first adaptive filter means having a reference input receiving said reference signal (r(n)) from said second means, a first error-control input receiving said output signal (S(n)), and a second error-control input receiving an estimation signal (S 1 (n)), for providing said noise reference signal (w(n)) responsive to a predetermined response pattern dependent upon the conditions of all of said signals then present at said reference input, said first error-control input and said second error-control input; second adaptive filter means having a reference input receiving said output signal (S(n)) and a single error-control input receiving an auxiliary signal (w 1 (n)) for providing said estimation signal (S 1 (n)) to said first adaptive filter means second error-control input; and second summer means for subtracting said estimation signal (S 1 (n)) from said reference signal (r(n)) to provide said auxiliary signal (W 1 (n)) to said second adapter filter means signal error-control input.

Claim 3

The adaptive noise canceller of claim 1, wherein said first adaptive filter means provides said noise-reference signal (w(n)) responsive to a set of filter coefficients (b k (n+1)), where k is each integer number between zero and a number N of equivalent first filter taps, said filter coefficient set being periodically modified both by the output signal (S(n)) at said first error-control input and by said estimation signal (S 1 (n)) at said second error-control input.

Claim 4

The adaptive noise canceller of claim 2, wherein the coefficients b k (n+1) of said first adaptive filter coefficient set are periodically modified in accordance with the formula: b.sub.k (n+1)=b.sub.k (n)+2μS(n)[r(n-k)-S1(n-k)] where μ is a first small positive step-size constant.

Claim 5

The adaptive noise canceller of claim 3, wherein said second adaptive filter means provides said auxiliary signal (w 1 (n)) responsive to another set of filter coefficients c k' (n+1), where k' is each integer number between zero and a number N' of equivalent second filter taps, said another filter coefficient set being periodically modified by said auxiliary signal (w 1 (n)) at said single error-control input.

Claim 6

The adaptive noise canceller of claim 4, wherein the number N of equivalent first filter taps is substantially equal to the number N' of equivalent second filter taps.

Claim 7

The adaptive noise canceller of claim 4, wherein the coefficients c k (n+1) of said second adaptive filter coefficient set are periodic modified in accordance with the formula: c.sub.k' (n+1)=c.sub.k' (n)+2μ'[r(n)-S.sub.1 (n)]·S(n-k') where μ' is a second small step-size constant.

Claim 8

The adaptive noise canceller of claim 6, wherein said first constant μ is substantially equal to said second constant μ'.

Claim 9

The adaptive noise canceller of claim 6, wherein said second adaptive filter means comprises a finite-impulse-response filter having a delay line of N' taps.

Claim 10

The adaptive noise canceller of claim 1, wherein said second adaptive filter means provides said auxiliary signal (w 1 (n)) responsive to a set of filter coefficients c k' (n+1), where k' is all integer numbers between zero and a number N' of equivalent second filter taps, said filter coefficient set being periodically modified by said auxiliary signal (w 1 (n)) at said single error-control input.

Claim 11

The adaptive noise canceller of claim 9, wherein the periodic modification of the set of second adaptive filter coefficients c k '(n+1) is in accordance with the formula: c.sub.k' (n+1)=c.sub.k' (n)+2μ'[r(n)-S.sub.1 (n)]·S(n-k') where μ' is a small step-size constant.

Claim 12

The adaptive noise canceller of claim 10, wherein said second adaptive filter means comprises a finite-impulse-response filter having a delay line of N' taps.

Claim 13

An adaptive noise canceller, comprising: microcontroller means for processing digital signals, said microcontroller means comprising at least a central processing unit and a plurality of register sets each containing at least one storage register of at least one storage location and at least two storage register sets for storing first and second adaptive filter coefficient sets b k and c k each having at least one coefficient term therein; first means, receiving from a first transducer a primary input analog signal, containing a first desired signal portion and a second undesired random noise signal portion and having a first ratio of the amplitudes of the desired signal to the noise signal, for converting said primary analog signal to a digitally-encoded primary signal at a rate responsive to at least one clock signal; second means, receiving from a second transducer, different from said first transducer, a reference input analog signal, having a first crosstalk signal portion with a time-amplitude characteristic similar to that of said first portion of said primary signal and having a second random noise portion with a time-amplitude characteristic similar to that of the second portion of said primary signal and having a crosstalk signal to noise signal amplitude ratio independent of the first ratio of the primary input analog signal, for converting said reference analog signal to a digitally-encoded reference signal at a rate responsive to said at least one clock signal; clock means for providing said first and second converting means with said at least one clock signal; memory means for storing a sequence of digital control signals to be sequentially provided to said microcontroller means responsive to requests therefrom, and for causing: (a) said microcontroller means to alternately obtain for storage in first and second register sets, respectively, the digitally-encoded primary and reference signals, respectively, from the respective first and second converting means; (b) to cause said microcontroller means to obtain, for storage in a third register set, at least one digital signal estimating the crosstalk speech portion in said reference signal; (c) for causing said microcontroller means to obtain, for storage in a fourth register set, at least one other signal estimating the noise portion of said reference signal; and (d) for causing said microcontroller means to then obtain, from the data in at least said first through fourth register sets and said first and second coefficient register sets, an output signal, for storage in a fifth register set, having the desired signal portion of said primary input and said second undesired portion of said primary input reduced in amplitude responsive to the reference signal noise portion estimation signal; and means receiving the reduced-noise-portion output signal from said fifth register set for providing a canceller output signal.

Claim 14

An adaptive noise canceller, comprising: microcontroller means for processing digital signals, said microcontroller means comprising at least a central processing unit and a plurality of register sets each containing at least one storage register of at least one storage location and at least two storage register sets for storing first and second adaptive filter coefficient sets b k and c k each having at least one coefficient term therein; first means, receiving from a first transducer a primary input analog signal, containing a first desired signal portion and a second undesired random noise signal portion and having a first ratio of the amplitudes of the desired signal to the noise signal, for converting said primary analog signal to a digitally-encoded primary signal at a rate responsive to at least one clock signal; second means, receiving from a second transducer, different from said first transducer, a reference input analog signal, having a first crosstalk signal portion with a time-amplitude characteristic similar to that of said first portion of said primary signal and having a second random noise portion with a time-amplitude characteristic similar to that of the second portion of said primary signal and having a crosstalk signal to noise signal amplitude ratio independent of the first ratio of the primary input analog signal, for converting said reference analog signal to a digitally-encoded reference signal at a rate responsive to said at least one clock signal; clock means for providing said first and second converting means with said at least one clock signal; memory means for storing a sequence of digital control signals to be sequentially provided to said microcontroller means responsive to requests therefrom, and for causing: (a) said microcontroller means to alternately obtain for storage in first and second register sets, respectively, the digitally-encoded primary and reference signals, respectively, from the respective first and second converting means; (b) to cause said microcontroller means to obtain, for storage in a third register set, at least one digital signal estimating the crosstalk speech portion in said reference signal; (c) for causing said microcontroller means to obtain, for storage in a fourth register set, at least one other signal estimating the noise portion of said reference signal; and (d) for causing said microcontroller means to then obtain, from the data in at least said first through fourth register sets and said first and second coefficient register sets, an output signal, for storage in a fifth register set, having the desired signal portion of said primary input and said second undesired portion of said primary input reduced in amplitude responsive to the reference signal noise portion estimation signal; and means receiving the reduced-noise-portion output signal from said fifth register set for providing a canceller output signal.

Claim 15

The adaptive noise canceller of claim 12, wherein said first means further comprises CODEC means for selectively filtering and then digitally-encoding, responsive to said at least one clock signal, said primary input analog signal.

Claim 16

The adaptive noise canceller of claim 13, wherein said CODEC means provides the digitally-encoded primary input signal as a serial data output signal having a series of sequential data bits.

Claim 17

The adaptive noise canceller of claim 14, wherein said microcontroller means has at least one parallel-data input port, said first means further including: means for converting the serial data output signal from said CODEC means to a parallel digital data format for introduction to said at least one data input port of said microcontroller means.

Claim 18

The adaptive noise canceller of claim 12, wherein said second means further comprises CODEC means for selectively filtering and then digitally-encoding, responsive to said at least one clock signal, said reference input analog signal.

Claim 19

The adaptive noise canceller of claim 16, wherein said CODEC means provides the digitally-encoded primary input signal as a serial data output signal having a series of sequential data bits.

Claim 20

The adaptive noise canceller of claim 17, wherein said microcontroller means has at least one parallel-data input port, said second means further including: means for converting the serial data output signal from the CODEC means to a parallel digital data format for introduction to said at least one data input port of said microcontroller means.

Claim 21

The adaptive noise canceller of claim 12, wherein said microcontroller means has at least one parallel-data output port and said output means further includes: means, receiving said output signal as a set of parallel data signals from said microcontroller output port, for converting said parallel digital data signals to a serial data bit stream which is provided as said canceller output signal.

Claim 22

The adaptive noise canceller of claim 12, wherein said memory means comprises: read-only memory (ROM) means having said digital control signals stored therein, but incapable of sequentially providing said digital control signals at a desired sequential rate responsive to requests therefor from said microcontroller means; random-access memory (RAM) means capable of providing said digital control signals at the desired sequential rate to said microcontroller means responsive to requests therefrom; and means for transferring the digital control signals stored in said ROM means to said RAM means upon commencement of operation of said adaptive noise canceller.

Claim 23

The adaptive noise canceller of claim 20, wherein said transferring means comprises: means for providing to said microcontroller means a first clock frequency, less than a desired microcontroller operating frequency at which the digital control signals are at said desired sequential rate, to cause said ROM means to be accessed at a first rate at the commencement of operation of said canceller and during transfer of the entirety of the digital control signals from said ROM means to said RAM means, and for then providing an operating clock frequency, greater than the first clock frequency, to said microcontroller means thereafter, to cause said digital control signals now stored in said RAM means to be provided to said microcontroller means responsive to requests therefrom, at a higher rate of transfer than possible from said ROM means.

Claim 24

The adaptive noise canceller of claim 21, wherein said clock means also provides said first clock frequency signal and said higher clock frequency signal.

Claim 25

The adaptive noise canceller of claim 12, wherein each of said at least two register sets for storing said first and second adaptive filter coefficient sets b k and c k store a predetermined number of coefficients sufficient to implement the equivalent of a finite-impulse-response filter having a preselected plurality of delay means taps.

Claim 26

The adaptive noise canceller of claim 23, wherein each of the first and second filter coefficient register sets stores a number of coefficients sufficient to implement a 16-tap delay-line filter.

Claim 27

The adaptive noise canceller of claim 12, wherein: the first coefficient set storage register stores the set of first coefficients b k (n), where k is each integer number between zero and a predetermined number N of equivalent first filter tops and n is one of a successive sequence of time intervals; and the microcontroller means is caused to periodically modify, during each time interval n, the set of first coefficients b k (n) to a set of first coefficients b k (n+1) in accordance with the formula b.sub.k (n+1)=b.sub.k (n)+2μS(n)[r(n=k)-S1(n-k)] where μ is a first small positive step-size constant, S(n) is output signal data provided from the fifth register set, r(n-k) is reference signal data provided from the second register set, and S1(n-k) is crosstalk speech portion data provided from the third register set.