US4649476A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer having an internal address mapper
Assignee: NXP USA Inc
•
Filing: 1983-10-31
•
Granted: 1987-03-10
•
Expires: 2003-10-31
Abstract
Abstract In a microcomputer, an address mapper allows the user to selectively map a resource which is ordinarily addressable in one portion of the address range of the microcomputer into a correspondingly sized area elsewhere in the address range. Using a resource map address stored by the user in an addressable map register, the mapper continuously compares the map address to a corresponding number of bits on the microcomputer's address bus. When a match is detected, the mapper enables the address decoder of the mapped resource. The mapper can also map the map register. Since the mapper can map more than one resource, an interlock mechanism resolves access conflicts.
Inventors
- 👤 James M. Sibigtroth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:57
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
226 words
In a microcomputer comprising: an address bus for communicating addresses comprising at least a first set of address bits and a second set of address bits; a first resource for performing a predetermined function in response to the coincidence of a first enable signal and a first predetermined address on said first set of address bits; and a second resource for performing a predetermined function in response to the coincidence of a second enable signal and a second predetermined address on said first set of address bits; an address mapper comprising: map register means for storing a first and second resource map address, each having the same number of bits as said second set of address bits; first comparator means coupled to said map register and to said address bus, for comparing said first resource map address to said second set of address bits, and for providing said first enable signal to said first resource only when said second set of address bits is identical to said first resource map address; and second comparator means coupled to said map register and to said address bus, for comparing said second resource map address to said second set of address bits, and for providing said second enable signal to said second resource only when said second set of address bits is identical to said second resource map address.
Claim 2
Dependent Claim
226 words
In a microcomputer comprising: an address bus for communicating addresses comprising at least a first set of address bits and a second set of address bits; a first resource for performing a predetermined function in response to the coincidence of a first enable signal and a first predetermined address on said first set of address bits; and a second resource for performing a predetermined function in response to the coincidence of a second enable signal and a second predetermined address on said first set of address bits; an address mapper comprising: map register means for storing a first and second resource map address, each having the same number of bits as said second set of address bits; first comparator means coupled to said map register and to said address bus, for comparing said first resource map address to said second set of address bits, and for providing said first enable signal to said first resource only when said second set of address bits is identical to said first resource map address; and second comparator means coupled to said map register and to said address bus, for comparing said second resource map address to said second set of address bits, and for providing said second enable signal to said second resource only when said second set of address bits is identical to said second resource map address.
Claim 3
Dependent Claim
57 words
The microcomputer of claim 1 wherein said address mapper means further comprises gate means interposed between said second comparator means and said second resource for providing said second enable signal to said second resource only in response to the coincidence of said second enable signal and of said enable signal provided by the first said comparator means.
Claim 4
Dependent Claim
91 words
The microcomputer of claim 1 wherein said address bus further comprises a third set of address bits, and wherein said address mapper further comprises gate means interposed between said second comparator means and said second resource for providing the second enable signal to said second resource only in response to the coincidence of said enable signal provided by the first of said comparators and of said second enable signal provided by said second comparator means and of a selected address on said third set of address bits of said address bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-09 | 1990-09-08 | 1991-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-09 | 1994-09-08 | 1995-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-09 | 1998-09-08 | 1999-03-10 | $7700.00 | Window Closed / Lapsed |