PNPN semiconductor switches

Claim 1

In a planar type PNPN semiconductor switch comprising: an N type monocrystalline semiconductor substrate acting as an N gate region; an anode region formed by diffusing a P type impurity into a surface of said semiconductor substrate; a P gate region spaced from said anode region by a predetermined distance and formed by diffusing a P type impurity into the surface of said semiconductor substrate; a combined source and cathode region formed by diffusing an N type impurity into a surface of said P gate region; a drain region spaced from said combined source and cathode region by a predetermined distance and formed by diffusing an N type impurity into said P gate region; a first gate electrode formed above said P gate region between said drain region and said combined source and cathode region via a first gate insulating layer; a second gate electrode formed over said first gate electrode via a second insulating layer; an anode electrode which is in ohmic contact with said anode region; a resistor arranged over the surface of said substrate and having one end connected to said first gate electrode and having another end connected to both said P gate region and said drain region; and a conductive layer disposed on an insulating layer for electrically interconnecting said anode electrode and said second gate electrode; the improvement which comprises a polycrystalline silicon field plate electrode extending under said conductive layer and over a PN junction between said P gate region and said N type substrate; one end of said field plate electrode being in contact with said combined source and cathode region and another end of said field plate electrode extending over the surface of said substrate between said anode region and said P gate region; said field plate electrode being isolated from said conductive layer and the surface of said substrate by insulating layers, whereby the extension of a depletion layer from said anode region to said P gate region is prevented.