US4647840A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit
Assignee: Toshiba Corp
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Filing: 1986-02-12
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Granted: 1987-03-03
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Expires: 2006-02-12
Abstract
Abstract A current mirror circuit which is not adversely effected by temperature changes and which is able to be operated by a relatively low D.C. power source voltage. The circuit includes a current source connected to the commonly connected bases of two transistors. A level shifting diode-connected transistor is connected between the current source and the collector of one of the two transistors. The base-emitter junction area of this level shifting transistor is greater than that of the first transistor so that the potential of the input node is low. The potential between the collector and emitter of the first transistor is determined by the difference in voltages of V be of the first transistor and the level shifting transistor. The circuit also includes either an additional current source or an additional level shifting transistor connected to the collector of the second transistor.
Inventors
- 👤 Satoshi Hiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:41
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
177 words
A current mirror circuit comprising: a power supply terminal; a reference voltage terminal; a first transistor of a first conductivity type having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal and the collector being connected to said power supply; a second transistor of the same conductivity type as said first transistor, having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal; said bases of said first and second transistors being connected to each other; the collector of said first transistor being connected to a current input node; current source means connected between said power supply terminal and said bases; load circuit means connected between said power supply terminal and the collector of said second transistor; and a third transistor being diode-connected, having a junction area greater than the base-emitter junction area of said first transistor, and being connected between said collector and said base of said first transistor to apply a current from said current source means to said current input node.
Claim 2
Dependent Claim
177 words
A current mirror circuit comprising: a power supply terminal; a reference voltage terminal; a first transistor of a first conductivity type having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal and the collector being connected to said power supply; a second transistor of the same conductivity type as said first transistor, having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal; said bases of said first and second transistors being connected to each other; the collector of said first transistor being connected to a current input node; current source means connected between said power supply terminal and said bases; load circuit means connected between said power supply terminal and the collector of said second transistor; and a third transistor being diode-connected, having a junction area greater than the base-emitter junction area of said first transistor, and being connected between said collector and said base of said first transistor to apply a current from said current source means to said current input node.
Claim 3
Dependent Claim
31 words
A current mirror circuit according to claim 1, wherein said load circuit means includes a second current source means connected between said power supply and the collector of said second transistor.
Claim 4
Dependent Claim
28 words
A current mirror circuit according to claim 1, wherein said load circuit means includes a resistor connected between said power supply and the collector of said second transistor.
Claim 5
Dependent Claim
17 words
A current mirror circuit according to claim 1, wherein said first and second transistors are NPN transistors.
Claim 6
Dependent Claim
223 words
A current mirror circuit comprising: a power supply terminal; a reference voltage terminal; a first transistor of a first conductivity type having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal and the collector being connected to said power supply; a second transistor of the same conductivity type as said first transistor, having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal; said bases of said first and second transistors being connected to each other; the collector of said first transistor being connected to a current input node; current source means connected between said power supply terminal and said bases; load circuit means connected between said power supply terminal and the collector of said second transistor; first diode junction means having a junction area greater than the base-emitter junction area of said first transistor, and being connected between the collector and the base of said first transistor to apply a current from said current source means to said current input node; and second diode junction means having a junction area greater than the base-emitter junction area of said second transistor, and being connected between the collector and the base of said second transistor to apply a current from said current source means to the collector of said second transistor.
Claim 7
Dependent Claim
223 words
A current mirror circuit comprising: a power supply terminal; a reference voltage terminal; a first transistor of a first conductivity type having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal and the collector being connected to said power supply; a second transistor of the same conductivity type as said first transistor, having an emitter, a base and a collector, the emitter being connected to said reference voltage terminal; said bases of said first and second transistors being connected to each other; the collector of said first transistor being connected to a current input node; current source means connected between said power supply terminal and said bases; load circuit means connected between said power supply terminal and the collector of said second transistor; first diode junction means having a junction area greater than the base-emitter junction area of said first transistor, and being connected between the collector and the base of said first transistor to apply a current from said current source means to said current input node; and second diode junction means having a junction area greater than the base-emitter junction area of said second transistor, and being connected between the collector and the base of said second transistor to apply a current from said current source means to the collector of said second transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-02 | 1990-09-01 | 1991-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-02 | 1994-09-01 | 1995-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-02 | 1998-09-01 | 1999-03-03 | $7700.00 | Window Closed / Lapsed |