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US4329639A Expired / Lapsed US ⏱️ 0.0 years remaining

Low voltage current mirror

Assignee: Motorola Solutions Inc
•
Filing: 1980-02-25
•
Granted: 1982-05-11
•
Expires: 2000-02-25
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Abstract

Abstract A highly accurate current mirror for IC implementation is comprised of low beta transistors and operates on a low supply voltage by utilizing a bias network with a balance sensing feedback network to control the bias voltage. The output current of one of the mirror transistors is compared with the reference current and the level of the current is then forced to equal the reference by means of the bias voltage adjustment.

Inventors

  • 👤 Walter L. Davis

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 05:57
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 143 words
A current mirror circuit usable with a single cell voltage supply and comprising: a voltage supply; a reference voltage source; first and second transistors of the same conductivity type with bases coupled together, the second transistor being coupled between the voltage supply and the reference voltage source and supplying an output current: a first current reference source coupled to the first transistor means; a resistor coupled to the voltage supply; diode means coupled between the resistor and the bases of the first and second transistors; an adjustable current source coupled between the bases of the first and second transistors and the reference voltage source; and a third transistor of said same conductivity type coupled between the resistor and the reference voltage source for forcing the output current to be a direct function of a reference current provided by said first current reference source.
Claim 2
Dependent Claim 143 words
A current mirror circuit usable with a single cell voltage supply and comprising: a voltage supply; a reference voltage source; first and second transistors of the same conductivity type with bases coupled together, the second transistor being coupled between the voltage supply and the reference voltage source and supplying an output current: a first current reference source coupled to the first transistor means; a resistor coupled to the voltage supply; diode means coupled between the resistor and the bases of the first and second transistors; an adjustable current source coupled between the bases of the first and second transistors and the reference voltage source; and a third transistor of said same conductivity type coupled between the resistor and the reference voltage source for forcing the output current to be a direct function of a reference current provided by said first current reference source.
Claim 3
Dependent Claim 18 words
A current mirror circuit in accordance with claim 1 wherein the diode means is a fourth, diode-connected transistor.
Claim 4
Dependent Claim 20 words
A current mirror circuit in accordance with claim 1 wherein the first, second and third transistor means are PNP transistors.
Claim 5
Dependent Claim 32 words
A current mirror circuit in accordance with claim 1 wherein the first current reference source includes a second current mirror and a second current reference source coupled to the second current mirror.
Claim 6
Dependent Claim 40 words
A current mirror circuit in accordance with claim 4 wherein the first current reference source also includes control means for varying the current of the first current reference source with respect to the current of the second current reference source.
Claim 7
Dependent Claim 22 words
A current mirror circuit in accordance with claim 4 wherein the second current reference source includes transistors of said same conductivity type.
Claim 8
Dependent Claim 19 words
A current mirror circuit in accordance with claim 1 wherein the second transistor means comprises a plurality of transistors.

References Cited (Backward Citations)

US3813607A Cited
US3843933A Cited
US4008441A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-05-10 1985-11-09 1986-05-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-05-10 1989-11-09 1990-05-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-05-10 1993-11-09 1994-05-11 $7700.00 Window Closed / Lapsed

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