Circuit arrangement for synchronizing of clock-signal generated at a receiving station with clock-signals received in telecommunications systems with digital transmission of information

Claim 1

In a digital data telecommunication system, a circuit arrangement for synchronizing the clock pulse signal generated at a receiving station with the received data signal, comprising: a first (FF1) and a second (FF2) bistable flip-flop each having a set input and a reset (R) input responsive to an edge of a pulse signal and each having a respectively corresponding set output (Q) and reset output; a monostable flip-flop (MF) for producing a fixed width output pulse (Te) in response to the leading edge of a received clock and data pulse signal (ES); a clock pulse generator (TG) for generating a clock pulse signal; means for feeding in part a clock pulse signal (T f ) from said clock pulse generator to the set input of said second bistable flip-flop and to the reset input of said first bistable flip-flop; first logical circuit means coupled to the set output (FF1Q) of said first flip-flop for changing the clock pulse generator control voltage to increase the frequency of said clock pulse generator signal; second logical circuit means coupled to the set output (FF2Q) of said second flip-flop for changing the clock pulse generator control voltage to decrease the frequency of said clock pulse generator signal; third logical circuit means coupled to the output of said monostable flip-flop for setting said first flip-flop and for preventing the generated clock pulse signal from setting said second flip-flop when the received clock and data pulse signal is earlier in phase relationship to the generated clock pulse signal and for preventing the setting of said first flip-flop and permitting the generated clock signal to set the second flip-flop when the received clock and data pulse signal is later in phase relationship to the generated clock pulse signal; a third bistable flip-flop (FF3) having a set and a reset input responsive to an edge of a pulse signal and having a respectively corresponding set output (FF3Q) and a reset output; fourth logical circuit means coupled to the outputs of said third flip-flop for preventing said first and second logical circuit means from changing the clock pulse generator control voltage to thereby prevent change in the frequency of said clock pulse generator signal when said third flip-flop is in the set condition; and fifth circuit means coupled to the set and reset inputs of said third flip-flop for setting said third flip-flop and holding it set during a prolonged gap in the received signal (ES).