Electronic phase detector having an output which is proportional to the phase difference between two data signals

Claim 2

A phase detecting circuit comprising: a first bistable circuit having a data input, a clock input, a reset input and a NOT Q output, wherein said first circuit data input is connected to a logic high signal and wherein said NOT Q output goes to a logic low state when a logic high signal is received at said first circuit clock input and said first circuit reset input is receiving a logic low signal, and said NOT Q output goes to a logic high state when a logic high signal is received at said first circuit reset input; a second bistable circuit having a data input, a clock input, a reset input, and a Q output, wherein said second circuit data input is connected to a logic high signal and wherein said Q output goes to a logic high state when a logic high signal is received at said second circuit clock input and said second circuit reset input is receiving a logic low signal, and said Q output goes to a logic low state when a logic high signal is received at said second circuit reset input; a first terminal for receiving a reference data signal; a second terminal for receiving a second data signal; means for connecting said first terminal to said first circuit reset input; means for connecting said second terminal to said first circuit clock input; a first inverting means connected between said first terminal and said second circuit clock input; and a second inverting means connected between said second terminal and said second circuit reset input; wherein the average value of the sum of voltages appearing on said Q and NOT Q outputs is proportional to the phase difference between the reference signal and the second signal.

Claim 3

A phase detecting circuit as recited in claim 1, further comprising: a voltage dividing circuit branch connected between said Q and NOT Q outputs.

Claim 4

A phase detecting circuit as recited in claim 2, wherein said voltage dividing circuit branch comprises: a pair of resistors electrically connected in series, wherein the average voltage appearing at the junction of said resistors is proportional to the phase difference between said reference data signal and said controlled data signal.

Claim 5

A phase detecting circuit comprising: a first terminal for receiving a reference data input signal; a second terminal for receiving a second data signal; a first type D flip-flop circuit; a second type D flip-flop circuit; means for connecting a logic high signal to the D inputs of said first and second flip-flop circuits; a first inverting means coupled between said first terminal and the clock input of said first flip-flop circuit; means for connecting said first terminal to the reset input of said second flip-flop circuit; a second inverting means coupled between said second terminal and the reset input of said first flip-flop circuit; means for connecting said second terminal to the clock input of said second flip-flop circuit; means for coupling the Q output of said first flip-flop circuit to an output terminal; and means for coupling the Q output of said second flip-flop circuit to said output terminal; wherein the average value of the sum of voltages appearing on said Q and Q outputs is proportional to the phase difference between the reference signal and the second signal.

Claim 6

A phase detecting circuit comprising: a first terminal for receiving a reference data input signal; a second terminal for receiving a second data signal; a first type D flip-flop circuit; a second type D flip-flop circuit; means for connecting a logic high signal to the D inputs of said first and second flip-flop circuits; a first inverting means coupled between said first terminal and the clock input of said first flip-flop circuit; means for connecting said first terminal to the reset input of said second flip-flop circuit; a second inverting means coupled between said second terminal and the reset input of said first flip-flop circuit; means for connecting said second terminal to the clock input of said second flip-flop circuit; means for coupling the Q output of said first flip-flop circuit to an output terminal; and means for coupling the Q output of said second flip-flop circuit to said output terminal; wherein the average value of the sum of voltages appearing on said Q and Q outputs is proportional to the phase difference between the reference signal and the second signal.

Claim 7

A phase detecting circuit as recited in claim 4, wherein said means for connecting the Q output of said first flip-flop circuit to said output terminal comprises a first resistor, and said means for connecting the Q output of said flip-flop circuit to said output terminal comprises a second resistor.

Claim 8

A phase detecting circuit as recited in claim 5, wherein said first and second resistors have equal resistance values.

Claim 9

A phase-locked loop circuit comprising: an input terminal for receiving a reference data signal; a second terminal for receiving a controlled data signal; a first bistable circuit having a data input, a clock input, a reset input and a NOT Q output, wherein said data input is connected to a logic high signal, said NOT Q output goes to a logic low state when a logic high clock pulse is received at said clock input and said reset input is receiving a logic low signal, and said NOT Q output goes to a logic high state when a logic high signal is received at said reset input; means for transmitting said reference data signal to the clock input of said first bistable circuit; means for transmitting said controlled data signal to the reset input of said first bistable circuit; a second bistable circuit having a data input, a clock input, a reset input and a Q output, wherein said data input is connected to a logic high signal, and Q output goes to a logic high state when a logic high clock pulse is received at said clock input and said reset input is receiving a logic low signal, and said Q output goes to a logic low state when a logic high signal is received at said reset input; means for inverting said reference data signal; means for transmitting the inverted reference data signal to the clock input of said second bistable circuit; means for inverting said controlled data signal; means for transmitting the inverted controlled data signal to the reset input of said second bistable circuit; a voltage divider circuit branch connected between said Q output of said second bistable circuit and said NOT Q output of said first bistable circuit, wherein the average voltage on an intermediate point on said voltage divider circuit branch varies linearly from a first predetermined voltage level to a second predetermined voltage level as the phase difference between said reference signal and said controlled data signal varies from -180° to +180°; means for shifting the magnitude of said average voltage by a fixed amount; means for integrating the shifted magnitude average voltage to obtain a frequency control signal; means for generating said controlled data signal in response to said frequency control signal; and means for coupling said controlled data signal to said second terminal.

Claim 10

A phase-locked loop circuit comprising: an input terminal for receiving a reference data signal; a second terminal for receiving a controlled data signal; a first bistable circuit having a data input, a clock input, a reset input and a NOT Q output, wherein said data input is connected to a logic high signal, said NOT Q output goes to a logic low state when a logic high clock pulse is received at said clock input and said reset input is receiving a logic low signal, and said NOT Q output goes to a logic high state when a logic high signal is received at said reset input; means for transmitting said reference data signal to the clock input of said first bistable circuit; means for transmitting said controlled data signal to the reset input of said first bistable circuit; a second bistable circuit having a data input, a clock input, a reset input and a Q output, wherein said data input is connected to a logic high signal, and Q output goes to a logic high state when a logic high clock pulse is received at said clock input and said reset input is receiving a logic low signal, and said Q output goes to a logic low state when a logic high signal is received at said reset input; means for inverting said reference data signal; means for transmitting the inverted reference data signal to the clock input of said second bistable circuit; means for inverting said controlled data signal; means for transmitting the inverted controlled data signal to the reset input of said second bistable circuit; a voltage divider circuit branch connected between said Q output of said second bistable circuit and said NOT Q output of said first bistable circuit, wherein the average voltage on an intermediate point on said voltage divider circuit branch varies linearly from a first predetermined voltage level to a second predetermined voltage level as the phase difference between said reference signal and said controlled data signal varies from -180° to +180°; means for shifting the magnitude of said average voltage by a fixed amount; means for integrating the shifted magnitude average voltage to obtain a frequency control signal; means for generating said controlled data signal in response to said frequency control signal; and means for coupling said controlled data signal to said second terminal.

Claim 11

A phase-locked circuit as recited in claim 7, wherein said voltage divider circuit branch comprises: a pair of resistors electrically connected in series, wherein said intermediate point is the common connection of said resistors.

Claim 12

A phase-locked loop circuit as recited in claim 7, wherein said means for shifting the magnitude of said average voltage comprises: a summing means which adds a fixed voltage to said average voltage.