Digital encoding and decoding apparatus

Claim 2

Digital input code decoding apparatus for decoding conforming input codes and non-conforming input codes, said apparatus comprising: (1) means for receiving input codes; and (2) decoding means, connected to said receiving means, said decoding means including first means, responsive to a received conforming input code, for producing an output code corresponding to said received input code, and second means, responsive to a received non-conforming input code, for producing an output code corresponding to a selected one of said conforming input codes.

Claim 3

The digital decoding apparatus of claim 1, wherein said second means further comprises means for determining the conforming input code most closely resembling said received non-conforming input code.

Claim 4

The digital decoding apparatus of claim 1 wherein said second means comprises means for selecting the conforming input code having a Hamming Distance of 1 from said received non-conforming input code.

Claim 5

The digital decoding apparatus of claim 1, further comprising: means for detecting a characteristic error in said input codes; and means for determining the conforming input code differing from said received non-conforming input code by said characteristic error.

Claim 6

The digital decoding apparatus of claim 1 wherein: said decoding means includes random-access memory means having an address input and a data output for storing a plurality of said output codes and outputting one of said output codes at said data output in response to an address at said address input; and said means for receiving input codes comprises means connected to said address input for providing any one of said input codes as a portion of said address to said random-access memory means, and wherein said output code output in response to said received non-conforming input code is one of said output codes corresponding to one of said conforming input codes.

Claim 7

Digital encoding apparatus for receiving an input data code and producing an output data code, corresponding to said input data code, said apparatus comprising: (1) random-access memory means, having an address input and a data output, for storing a plurality of code-status words and outputting at said data output the one of said code-status words corresponding to the address provided at said address input, each one of said code-status words containing a code part representing said output data code and a state part; (2) means, connected to said data output and said address input, for providing a first portion of the input address to said memory means, said register means including means for receiving said state part from said data output and means for outputting said received state part to said address input as first certain bits of said address; and (3) means connected to said address input for providing said input data codes as second certain bits of said address.

Claim 8

Digital encoding apparatus for receiving an input data code and producing an output data code, corresponding to said input data code, said apparatus comprising: (1) random-access memory means, having an address input and a data output, for storing a plurality of code-status words and outputting at said data output the one of said code-status words corresponding to the address provided at said address input, each one of said code-status words containing a code part representing said output data code and a state part; (2) means, connected to said data output and said address input, for providing a first portion of the input address to said memory means, said register means including means for receiving said state part from said data output and means for outputting said received state part to said address input as first certain bits of said address; and (3) means connected to said address input for providing said input data codes as second certain bits of said address.

Claim 9

In the digital encoding apparatus of claim 6, and wherein: at least one bit in said code-status word is common to both said code part and said state part whereby the number of bits in said code-status word is less than the sum of the number of bits in said code part and the number of bits in said state part.

Claim 10

Digital encoding and decoding apparatus for (a) receiving a first data code and encoding said first data code to produce a second data code corresponding to said first data code and (b) receiving said second data code and decoding said second data code to produce a first data code corresponding to said second data code, said digital encoding-decoding apparatus comprising: (1) random-access memory means having an address input and a data output for storing code status words including a first plurality of first code status words and a second plurality of second code status words and outputting one of said code status words at said data output in response to the corresponding address at said address inputs, each one of said first code status words containing a first data part representing said second data code and a first state part and each one of said second code status words containing a second data part representing said first data code and a second state part; (2) means connected to said data output and said address input for providing first certain bits of said address, said first certain bits including said first state part when said code status word last output by said random-access memory means is one of said first plurality of said first code status words and said second state part when said code status word last output by said random-access memory means is one of said second plurality of said second code status words; and (3) means connected to said input means for providing (a) a second certain bit of said address specifying which of said plurality of code status words is to be addresses, and (b) third certain bits of said address containing (i) said first data code when said second certain bit specifies said first plurality of said first code status words and (ii) said second data code when said second certain bit specifies said second plurality of said second code status words.

Claim 11

Digital encoding and decoding apparatus for (a) receiving a first data code and encoding said first data code to produce a second data code corresponding to said first data code and (b) receiving said second data code and decoding said second data code to produce a first data code corresponding to said second data code, said digital encoding-decoding apparatus comprising: (1) random-access memory means having an address input and a data output for storing code status words including a first plurality of first code status words and a second plurality of second code status words and outputting one of said code status words at said data output in response to the corresponding address at said address inputs, each one of said first code status words containing a first data part representing said second data code and a first state part and each one of said second code status words containing a second data part representing said first data code and a second state part; (2) means connected to said data output and said address input for providing first certain bits of said address, said first certain bits including said first state part when said code status word last output by said random-access memory means is one of said first plurality of said first code status words and said second state part when said code status word last output by said random-access memory means is one of said second plurality of said second code status words; and (3) means connected to said input means for providing (a) a second certain bit of said address specifying which of said plurality of code status words is to be addresses, and (b) third certain bits of said address containing (i) said first data code when said second certain bit specifies said first plurality of said first code status words and (ii) said second data code when said second certain bit specifies said second plurality of said second code status words.

Claim 12

The digital encoding and decoding apparatus of claim 8, and wherein: at least one bit in said code-status word is common to both said first code part and said first state part, whereby the number of bits in said first code-status word is less than the sum of the number of bits in said first code part and the number of bits in said first state part.

Claim 13

In the digital encoding and decoding apparatus of claim 8, and wherein: first certain ones of said second codes are non-conforming and second certain ones of said second codes are conforming; and said second code-status word corresponding to any of said non-conforming second codes contains said second code part corresponding to one of said conforming second codes, whereby said digital encoding apparatus produces said first codes from said non-conforming second codes.

Claim 14

In the digital encoding and decoding apparatus of claim 10, and wherein: said second code-status word corresponding to any of said non-conforming second codes contains said code part corresponding to said conforming second code most closely resembling said non-conforming second code.

Claim 15

In the digital encoding and decoding apparatus of claim 11, and wherein: said conforming second code most closely resembling said non-conforming second code is said conforming second code having a Hamming Distance of 1 from said non-conforming second code.

Claim 16

In the digital encoding and decoding apparatus of claim 11, and wherein: said second codes are obtained from a source producing a characteristic error in said second codes; and said conforming second code most closely resembling said non-conforming second code differs from said non-conforming second code by said characteristic error.

Claim 17

Digital decoding apparatus for receiving an input data code and producing an output data code corresponding to said input data code, said apparatus comprising: (1) random-access memory means, having an address input and a data output, for storing a plurality of code-status words and outputting at said data output the one of said code-status words corresponding to the address provided at said address input, each one of said code-status words containing a code part representing said output data code and a state part; (2) means, connected to said data output and said address input, for providing a first portion of the input address to said memory means, said register means including means for receiving said state part from said data output and means for outputting said received state part to said address input as first certain bits of said address; and (3) means connected to said address input for providing said input data codes as second certain bits of said address.

Claim 18

Digital decoding apparatus for receiving an input data code and producing an output data code corresponding to said input data code, said apparatus comprising: (1) random-access memory means, having an address input and a data output, for storing a plurality of code-status words and outputting at said data output the one of said code-status words corresponding to the address provided at said address input, each one of said code-status words containing a code part representing said output data code and a state part; (2) means, connected to said data output and said address input, for providing a first portion of the input address to said memory means, said register means including means for receiving said state part from said data output and means for outputting said received state part to said address input as first certain bits of said address; and (3) means connected to said address input for providing said input data codes as second certain bits of said address.

Claim 19

In the digital decoding apparatus of claim 14, and wherein: first certain ones of said input codes are non-conforming and second certain ones of said input codes are conforming; and said code-status word corresponding to any of said non-conforming input codes and said first state contains said code part corresponding to one of said conforming input codes, whereby said digital encoding apparatus decodes said output codes corresponding to said conforming input codes from said non-conforming input codes.

Claim 20

In the digital decoding apparatus of claim 15, and wherein: said code-status word corresponding to any of said non-conforming input codes contains said code part corresponding to said conforming input code most closely resembling said non-conforming input code.

Claim 21

In the digital decoding apparatus of claim 16, and wherein: said conforming input code most closely resembling said non-conforming input code is said conforming input code having a Hamming Distance of 1 from said non-conforming input code.

Claim 22

In the digital decoding apparatus of claim 16, and wherein: said input codes are obtained from a source producing a characteristic error in said input codes; and said conforming input code most closely resembling said non-conforming input code differs from said non-conforming input code by said characteristic error.