Solid state memory for aircraft flight data recorder systems

Claim 2

A solid state memory for storing digitally encoded flight data comprising: memory means having a power input terminal for applying an operating potential to said memory means and having a plurality of storage locations that are selectively accessed by supplying a digitally encoded address signal to said memory means, said memory means being responsive to a control signal for storing supplied digitally encoded data at storage locations corresponding to said address signal supplied to said memory means when said operating potential is supplied to said power input terminal and said control signal is supplied to said memory means; switch means having an input terminal, an output terminal and a control terminal, said output terminal of said switch means being coupled to said power input terminal of said memory means, said switch means being responsive to a switch control signal for coupling an electrical potential supplied to said input terminal of said switch means to said switch means output terminal only when said switch control signal is supplied to said control terminal of said switch means; and memory controller means for supplying said switch control signal to said switch means and for supplying said address signals and said control signal to said memory means, said memory controller means including means for executing an operational sequence wherein said address and control signals are periodically supplied to said memory means and wherein said switch control signal is supplied to said switch means only during periods of time in which said address and control signal is supplied to said memory means.

Claim 3

The solid state memory of claim 1 wherein said memory means and said memory controller means are contained within an environmental housing to thermally insulate said memory means and said memory controller means from the surrounding environment, and wherein said switch means is located outside said environmental housing.

Claim 4

The solid state memory of claim 1 wherein said memory controller means further includes means responsive to an applied interrupt signal for interrupting said operational sequence of said memory controller means, said solid state memory comprising power monitor means for monitoring an applied signal representative of the operating potential supplied to said input terminal of said switch means, said power monitor means including means for supplying said interrupt signal to said memory controller means when the level of said applied signal is less than a predetermined value.

Claim 5

The solid state memory of claim 3 wherein said memory means and said memory controller means are contained within an environmental housing to thermally insulate said memory means and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are located outside said environmental housing.

Claim 6

The solid state memory of claim 3 wherein said memory means includes means responsive to said control signal for enabling digital data transfer between said memory controller means and said selectively accessed storage locations when the magnitude of said control signal is within a predetermined range and for disabling digital data transfer between said memory controller means and said selectively accessed storage locations when said magnitude of said control signal is outside said predetermined range, said solid state memory further comprising memory protection means connected for receiving said interrupt signal supplied by said power monitor means, said memory protection means including means for supplying said control signal to said memory means at a magnitude within said predetermined range when said interrupt signal is not supplied to said memory protection means and means for supplying said control signal to said memory controller means at a magnitude that is outside said predetermined range when said interrupt signal is supplied to said memory protection means.

Claim 7

The solid state memory of claim 5 wherein said memory means, said memory protection means and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said memory protection means and said memory controller means from the surrounding environment, and wherein means from the surrounding environment, and wherein said switch means and said power monitor means are located outside said environmental housing.

Claim 8

The solid state memory of claim 5 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 9

The solid state memory of claim 7 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 10

The solid state memory of claim 5 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 11

The solid state memory of claim 3 wherein said memory controller means is responsive to a reset signal for initializing said operational sequence of said memory controller means and said power monitor means further comprises means responsive to said electrical potential supplied at said output terminal of said switch means for supplying said reset signal to said memory controller means when said operating potential for said memory means is not present at said output terminal of said switch means for a predetermined period of time.

Claim 12

The solid state memory of claim 10 wherein said memory means and said memory controller means are contained within an environmental housing to thermally insulate said memory means and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are located outside said environmental housing.

Claim 13

The solid state memory of claim 10 wherein said power monitor means further comprises means responsive to said opeerating potential supplied to said input terminal of said switch means for supplying a reset signal to said memory controller means each time operating potential is supplied to said input terminal of said switch means.

Claim 14

The solid state memory of claim 12 wherein said memory means and said memory controller means are contained within an environmental housing to thermally insulate said memory means and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are located outside said environmental housing.

Claim 15

The solid state memory of claim 12 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 16

The solid state memory of claim 14 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 17

The solid state memory of claim 10 wherein said memory means includes means responsive to said control signal for enabling digital data transfer between said memory controller means and said selectively accessed storage locations when the magnitude of said control signal is within a predetermined range and for disabling digital data transfer between said memory controller means and said selectively accessed storage locations when said magnitude of said control signal is outside said predetermined range, said solid state memory further comprising memory protection means connected for receiving said interrupt signal supplied by said power monitor means, said memory protection means including means for supplying said control signal to said memory means at a magnitude within said predetermined range when said interrupt signal is not supplied to said memory protection means and means for supplying said control signal to said memory controller means at a magnitude that it outside said predetermined range when said interrupt signal is supplied to said memory protection means.

Claim 18

The solid state memory of claim 16 wherein said memory means, said memory protection means, said means for temporarily storing said digitally encoded data and said memory controller means are contained within an environmental housing to thermally insulate said memory means and said memory controller means from the surrounding environment, and wherein said switch means is located outside said environmental housing.

Claim 19

The solid state memory of claim 16 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 20

The solid state memory of claim 18 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 21

The solid state memory of claim 16 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 22

The solid state memory of claim 10 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 23

The solid state memory of claim 21 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 24

The solid state memory of claim 10 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 25

The solid state memory of claim 3 wherein said memory controller means is responsive to a reset signal for initializing said operational sequence of said memory controller means and said power monitor means further comprises means responsive to said operating potential supplied to said input terminal of said switch means for supplying a reset signal to said memory controller means each time said operating potential is supplied to said input terminal of said switch means.

Claim 26

The solid state memory of claim 24 wherein said memory means and said memory controller means are contained within an environmental housing to thermally insulate said memory means and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are located outside said environmental housing.

Claim 27

The solid state memory of claim 24 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 28

The solid state memory of claim 26 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 29

The solid state memory of claim 24 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 30

The solid state memory of claim 3 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 31

The solid state memory of claim 29 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 32

The solid state memory of claim 3 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent vaues of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 33

The solid state memory of claim 1 wherein: (a) said memory controller means includes means for receiving digitally encoded data signals and for supplying said received digitally encoded signals to said memory means during said operational sequence of said memory controller means; (b) said solid state memory includes means for temporarily storing said digitally encoded data signals supplied by said memory controller means to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is dedicated for storing the addresses of other storage locations within said memory that do not properly store digitally encoded data coupled thereto when said controller means supplies said control signal to said memory means; and (d) said memory controller means includes means for: (1) reading the data stored in the storage locations being addressed each time said memory controller means supplies said control signal to said memory means, (2) comparing the data read from said addressed storage locations with the data stored in said means for temporarily storing said data signals, (3) storing the addresses of addressed storage locations in said predetermined set of dedicated storage locations of said memory means when said data read from said addressed storage locations does not correspond to said data stored in said means for temporarily storing said data signals, (4) comparing each of said address signals supplied by said memory controller means with said addresses stored in said predetermined set of dedicated storage locations, and (5) generating a different address signal each time said address supplied by said memory controller means is identical to one of said addresses stored in said predetermined set of dedicated storage locations.

Claim 34

The solid state memory of claim 32 wherein said memory means, said means for temporarily storing said digitally encoded data signals and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temporarily storing said digitally encoded data and said memory controller means from the surrounding environment, and wherein said switch means is located outside said environmental housing.

Claim 35

The solid state memory of claim 32 wherein said memory controller means further includes means responsive to an applied interrupt signal for interrupting said operational sequence of said memory controller means, said crash survivable solid state memory comprising power monitor means for monitoring an applied signal representative of the operating potential supplied to said input terminal of said switch means, said power monitor means including means for supplying said interrupt signal to said memory controller means when the level of said applied signal is less than a predetermined value.

Claim 36

The solid state memory of claim 34 wherein said memory means, said means for temporarily storing said digitally encoded data signals and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temporarily storing said digitally encoded data and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are located outside said environmental housing.

Claim 37

The solid state memory of claim 34 wherein said memory means includes means responsive to said control signal for enabling digital data transfer between said memory controller means and said selectively aaccessed storage locations when the magnitude of said control signal is within a predetermined range and for disabling digital data transfer between said memory controller means and said selectively accessed storage locations when said magnitude of said control signal is outside said predetermined range, said solid state memory further comprising memory protection means connected for receiving said interrupt signal supplied by said power monitor means, said memory protection means including means for supplying said control signal to said memory means at a magnitude within said predetermined range when said interrupt signal is not supplied to said memory protection means and means for supplying said control signal to said memory controller means at a magnitude that is outside said predetermined range when said interrupt signal is supplied to said memory protection means.

Claim 38

The solid state memory of claim 36 wherein said memory means, said memory protection means, said means for temporarily storing said digitally encoded data and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said memory protection means, said means for temporarily storing said digitally encoded data and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are located outside said environmental housing.

Claim 39

The solid state memory of claim 36 wherein said memory controller means is responsive to a reset signal for initializing said operational sequence of said memory controller means and said power monitor means further includes means responsive to said electrical potential supplied at said output terminal of said switch means for supplying said reset signal to said memory controller means when said operating potential for said memory means is not present at said output terminal of said switch means for a predetermined period of time.

Claim 40

The solid state memory of claim 38 wherein said memory means, said means for temporarily storing said digitally encoded data and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temporarily storing said digitally encoded data and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are outside said environmental housing.

Claim 41

The solid state memory of claim 36 wherein said memory controller means is responsive to a reset signal for initializing said operational sequence of said memory controller means and said power monitor means further comprises means responsive to said operating potential supplied to said input terminal of said switch means for supplying a reset signal to said memory controller means each time said operating potential is supplied to said input terminal of said switch means.

Claim 42

The solid state memory of claim 40 wherein said memory means, said means for temporarily storing said digitally encoded data and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temporarily storing said digitally encoded data and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are mounted outside said environmental housing.

Claim 43

The solid state memory of claim 40 wherein said power monitor means further includes means responsive to said electrical potential supplied at said output terminal of said switch means for supplying said reset signal to said memory controller means when said operating potential for said memory means is not present at said output terminal of said switch means for a predetermined period of time.

Claim 44

The solid state memory of claim 42 wherein said memory means, said means for temporarily storing said digital data and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temporarily storing said digital data and said memory controller means from the surrounding environment, and wherein said switch means is mounted outside said environmental housing.

Claim 45

The solid state memory of claim 40 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 46

The solid state memory of claim 44 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 47

The solid state memory of claim 36 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 48

The solid state memory of claim 34 wherein said memory controller means is responsive to a reset signal for initializing said operational sequence of said memory controller means and said power monitor means further includes means responsive to said electrical potential supplied at said output terminal of said switch means for supplying said reset signal to said memory controller means when said operating potential for said memory means is not present at said output terminal of said switch means for a predetermined period of time.

Claim 49

The solid state memory of claim 47 wherein said memory means, said means for temporarily storing said digitally encoded data and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temorarily storing said digitally encoded data and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are outside said environmental housing.

Claim 50

The solid state memory of claim 34 wherein said switch controller means is responsive to a reset signal for initializing said operational sequence of said memory controller means and said power monitor means further comprises means responsive to said operating potential supplied to said input terminal of said switch means for supplying a reset signal to said memory controller means each time said operating potential is supplied to said input terminal of said switch means.

Claim 51

The solid state memory of claim 49 wherein said memory means, said means for temporarily storing said digitally encoded data and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temporarily storing said digitally encoded data and said memory controller means from the surrounding environment, and wherein said switch means and said power monitor means are mounted outside said environmental housing.

Claim 52

The solid state memory of claim 49 wherein said power monitor means further includes means responsive to said electrical potential supplied at said output terminal of said switch means for supplying said reset signal to said memory controller means when said operating potential for said memory means is not present at said output terminal of said switch means for a predetermined period of time.

Claim 53

The solid state memory of claim 51 wherein said memory means, said means for temporarily storing said digital data and said memory controller means are contained within an environmental housing to thermally insulate said memory means, said means for temporarily storing said digital data and said memory controller means from the surrounding environment, and wherein said switch means is mounted outside said environmental housing.

Claim 54

The solid state memory of claim 34 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 55

The solid state memory of claim 53 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 56

The solid state memory of claim 34 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 57

The solid state memory of claim 32 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 58

The solid state memory of claim 56 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 59

The solid state memory of claim 32 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means further includes means for storing each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means is configured and arranged to supply said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 60

The solid state memory of claim 1 wherein said digitally encoded flight data are a sequence of digitally encoded data signals and wherein: (a) the decimal equivalent values of the digitally encoded address signals supplied to said memory means by said memory controller means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of data signals in said memory means; (b) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to address signals supplied to said memory means; (c) a predetermined set of said plurality of storage locations of said memory means is reserved for storing address pairs consisting of a first address that corresponds to the storage location address at which a selected one of said digitally encoded data signals of said sequence of signals is stored and a second address that corresponds to the storage location address at which a subsequent digitally encoded data signal of said sequence of signals is stored; and (d) said memory controller means further includes means for supplying said second control signal only for storage location addresses having a decimal equivalent value that is outside the range of consecutive integers that is defined by the decimal equivalent values of said first and second address for each of said address pairs.

Claim 61

The solid state memory of claim 59 wherein: (a) each said digitally encoded data signal of said sequence of signals exhibits a predetermined maximum bit length; (b) said memory controller means includes means for storing each digitally encoded signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (c) said memory means is configured and arranged to supply said second control signal for erasing a set of storage locations in said memory means prior to storage of each digitally encoded data signal of said sequence of said signals, said set of erased storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.

Claim 62

The solid state memory of claim 1 wherein: (a) said digitally encoded flight data are a sequence of signals with each data signal of said sequence having a maximum bit length; (b) the decimal equivalent values of the digitally encoded address signals supplied to said memory means are a set of consecutive integers ranging from 0 to n and said operational sequence of said memory controller means includes repeatedly accessing the storage locations of said memory means in ascending order relative to said decimal equivalent values of said address signals to store said digitally encoded data signals of said sequence of signals in said memory means; (c) said memory controller means further includes means for supplying a second control signal for erasing data stored at storage locations corresponding to said address signals supplied to said memory means; (d) said memory controller means in configured and arranged to store each digitally encoded data signal of said sequence of signals in a set of storage locations of said memory means at least equal in bit length to said predetermined maximum bit length; and (e) said memory means includes means for supplying said second control signal to said memory means for erasing a set of storage locations in said memory means prior to storage of each particular digitally encoded data signal of said sequence, said set of erase storage locations including storage locations that will store the next most digitally encoded data signal of said sequence of digitally encoded data signals.