Integrated circuits

Claim 1

An MOS compatible bipolar transistor structure comprising an npn lateral high gain transistor and an npn vertical low gain transistor formed in a lightly doped n - -type well in a major surface of a very lightly doped p -- -type substrate, the structure comprising a lightly doped p - -type well found in the n - -type well, a p + -region and p-type region formed in the p - -type well, a first n + -type region formed in said p-type region, and a second n + -type region formed at the surface boundary between the p - -type well and the n - -type well, wherein said first n + -type region provides a common emitter of both said transistors, wherein said second n + -type region provides the collector of the lateral transistor and a collector contact of the vertical transistor, wherein said p + -type region provides a base contact of both said transistors, wherein said p-type region provides the base of the lateral transistor and, together with the p - -type well, the base of the vertical transistor, and wherein a depletion region is disposed across the boundary between the p - -type and n - -type wells, the boundary being narrow adjacent the lateral transistor base so as to provide a high lateral gain and wide adjacent the vertical transistor base so as to provide a low vertical gain, whereby the structure, in use, acts predominantly in a lateral mode.