Apparatus and method for implementing dilation and erosion transformations in grayscale image processing

Claim 2

An image processing system for processing at least one start grayscale image each made up of a matrix of points, said system comprising: serializing means for producing at least one first serial signal including a plurality of multi-bit words each corresponding to one of the points of the associated start image; delay means for delaying selected ones of the first signals to produce at least one delayed serial signal each corresponding to one of the first signals, said delay means including adder means for adding a desired value to each word delayed by said delay means; and operating means for performing operations on selected ones of the delayed signals and the first signals to produce at least one output serial signal.

Claim 3

A system as defined in claim 1 wherein said operating means comprises means for performing logical operations on one of the delayed signals and one of the first signals.

Claim 4

A system as defined in claim 2 wherein said logical operating means comprises means for selecting the maximum of the one delay signal and the one first signal.

Claim 5

A geometric logic unit for processing at least one start serial signal each representative of a grayscale image made up of a matrix of points to produce at least one processed serial signal each representative of a processed grayscale image, each serial signal including a plurality of multi-bit words each corresponding to one of the points and having a value representative of the intensity of the one point, said geometric logic unit comprising a plurality of serially coupled stages each in turn comprising: input port means for receiving at least one input serial signal; delay means for delaying selected ones of the input signals to produce at least one delayed serial signal each corresponding to one of the input signals; adder means for adding a preselected value to each word of each delayed serial signal to produce at least one modified delayed serial signal each corresponding to one of the delayed serial signals; means for combining selected ones of the modified delayed serial signals and the input signals to produce at least one output serial signal; and output port means for outputting the output signals.

Claim 6

A geometric logic unit for processing at least one start serial signal each representative of a grayscale image made up of a matrix of points to produce at least one processed serial signal each representative of a processed grayscale image, each serial signal including a plurality of multi-bit words each corresponding to one of the points and having a value representative of the intensity of the one point, said geometric logic unit comprising a plurality of serially coupled stages each in turn comprising: input port means for receiving at least one input serial signal; delay means for delaying selected ones of the input signals to produce at least one delayed serial signal each corresponding to one of the input signals; adder means for adding a preselected value to each word of each delayed serial signal to produce at least one modified delayed serial signal each corresponding to one of the delayed serial signals; means for combining selected ones of the modified delayed serial signals and the input signals to produce at least one output serial signal; and output port means for outputting the output signals.

Claim 7

A geometric logic unit as defined in claim 4 wherein said combining means comprises means for logically combining the selected ones of the delayed signals and the input signals.

Claim 8

A geometric logic unit as defined in claim 5 wherein said logical combining means comprises means for selecting the maximum of the selected ones of the delayed signals.

Claim 9

A geometric logic unit for processing a serial signal including words representative of a grayscale image made up of a matrix of points to produce a serial signal representation of a dilation of the image, said geometric logic unit comprising a plurality of serially coupled stages each including: delay means for delaying an input signal inputted thereto to produce a delayed signal; adder means for increasing the value of each word in the delayed signal by a fixed amount to produce a supplemented delayed signal; and means for logically combining the input signal and the supplemented delayed signal to produce an output signal.

Claim 10

A geometric logic unit for processing a serial signal including words representative of a grayscale image made up of a matrix of points to produce a serial signal representation of a dilation of the image, said geometric logic unit comprising a plurality of serially coupled stages each including: delay means for delaying an input signal inputted thereto to produce a delayed signal; adder means for increasing the value of each word in the delayed signal by a fixed amount to produce a supplemented delayed signal; and means for logically combining the input signal and the supplemented delayed signal to produce an output signal.

Claim 11

A geometric logic unit as defined in claim 7 wherein said combining means comprises means for selecting the maximum of the inputted and supplemented delayed signals on a word-by-word basis.

Claim 12

A geometric logic unit as defined in claim 7 wherein said delaying means comprises a programmable delay circuit for selectively delaying an input signal applied thereto.

Claim 13

A geometric logic unit as defined in claim 9 wherein said adder means comprises a programmable adder for adding a selected value to the words in the delayed signal.

Claim 14

A geometric logic unit as defined in claim 7 wherein said adder means comprises a programmable adder for adding a selected value to the words in the delayed signal.

Claim 17

A system as defined in claim 12 wherein said combining means comprises means for logically combining the first serial signal and the altered delay serial signal.

Claim 18

A system as defined in claim 13 wherein said logical combining means comprises means for selecting the maximum of the first serial signal and the altered delay signal.

Claim 19

A system as defined in claim 12 wherein said system comprises a plurality of stages each including one of said delay means, one of said adder means, and one of said combining means; and further comprising control means for routing the serial signal sequentially through said plurality of stages.

Claim 22

A method as defined in claim 16 wherein said combining step comprises performing logical operations on one of the modified delayed signals and one of the input signals.

Claim 23

A method as defined in claim 17 wherein said performing step comprises selecting the maximum of the one modified delay signal and the one input signal to produce a first output signal.

Claim 26

A method as defined in claim 19 wherein said operating step comprises logically operating on one of the modified delayed serial signals and one of the input serial signals to produce the output signal.

Claim 27

A method as defined in claim 20 wherein said logically operating step comprises selecting the greater of the one modified delayed serial signal and the one input serial signal.

Claim 30

A method as defined in claim 22 wherein each of said combining steps comprises selecting the maximum of the input and supplemented delayed signals on a word-by-word basis.

Claim 33

A method as defined in claim 24 wherein said method comprises a plurality of step groups each comprising one of said shifting steps, one of said adding steps, and one of said combining steps; and wherein said method further comprises routing said first serialized signal sequentially through said plurality of step groups.

Claim 34

A method as defined in claim 25 wherein each of said shifting steps comprises delaying the serial signal inputted to the associated step group.

Claim 35

A method as defined in claim 26 wherein each of said combining steps comprises logically combining the signals inputted to and delayed by the associated step group on a word-by-word basis.

Claim 36

A method as defined in claim 27 wherein said logically combining step comprises selecting the maximum of the signals inputted to and delayed by the associated step group on a word-by-word basis.

Claim 37

A method as defined in claim 25 wherein each of said combining steps comprises logically combining the signals inputted to and shifted by the associated step group on a word-by-word basis.

Claim 38

A method as defined in claim 29 wherein said logically combining step comprises selecting the maximum of the signals inputted to and delayed by the associated step group on a word-by-word basis.