Patent US4641285A successfully refreshed from Google Patents.
US4641285A
Expired / Lapsed
US
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Line change-over circuit and semiconductor memory using the same
Assignee: Hitachi Ltd
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Filing: 1984-08-13
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Granted: 1987-02-03
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Expires: 2004-08-13
Abstract
Abstract The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission lines, first and second switch elements. The paired transfer gate elements are controlled on a switch in complementary manner each other according to a transfer signal. The first switch element is controlled on a switch according to the transfer signal, and the second switch element is controlled on a switch according to the first signal transmitted to one of the paired transmission lines. The first switch element turns one of the transmission lines to a fixed potential like ground potential when it is kept on, and the second switch element turns the other of the transmission lines to a fixed potential when it is kept on. The line change-over circuit in the above configuration is effective to prevent a floating state of the paired transmission lines.
Inventors
- 👤 Yukio Sasaki
- 👤 Kotaro Nishimura
- 👤 Osamu Minato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:38
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C8/00; G11C8/08
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
144 words
A line change-over circuit, comprising: a first node to which a first signal to be transmitted is supplied; a first transfer gate provided between said first node and a second node and operating as a switch according to a transfer signal; a second transfer gate provided between said first node and a third node and operating as a switch in a complementary manner to said first transfer gate according to said transfer signal; a first switch element coupled to said second node and turning said second node to a first fixed potential when said first transfer gate is kept off, said first switch element being operated as a switch according to said transfer signal; and a second switch element coupled to said third node and turning said third node to a second fixed potential when said first signal is supplied to said second node.
Claim 2
Dependent Claim
144 words
A line change-over circuit, comprising: a first node to which a first signal to be transmitted is supplied; a first transfer gate provided between said first node and a second node and operating as a switch according to a transfer signal; a second transfer gate provided between said first node and a third node and operating as a switch in a complementary manner to said first transfer gate according to said transfer signal; a first switch element coupled to said second node and turning said second node to a first fixed potential when said first transfer gate is kept off, said first switch element being operated as a switch according to said transfer signal; and a second switch element coupled to said third node and turning said third node to a second fixed potential when said first signal is supplied to said second node.
Claim 3
Dependent Claim
23 words
A line change-over circuit as defined in claim 1, wherein said first fixed potential and second fixed potential are equal with each other.
Claim 4
Dependent Claim
28 words
A line change-over circuit as defined in claim 2, wherein said second switch element coupled to said third node operates as a switch according to said first signal.
Claim 5
Dependent Claim
39 words
A line change-over circuit as defined in claim 2, further comprising a retaining circuit coupled to said third node and giving a positive feedback signal to said third node by referring to a signal level of said third node.
Claim 6
Dependent Claim
55 words
A line change-over circuit as defined in claim 1, wherein said first transfer gate is constituted of a first channel conductive insulating gate field effect transistor, and said second transfer gate, first and second switch elements are constituted each of a channel conductive insulating gate field effect transistor contrary to said first channel conductive one.
Claim 7
Dependent Claim
190 words
A semiconductor memory, comprising; a first node to which a selection signal formed according to address signals is supplied; a line change-over circuit provided between said first node and second and third nodes, which comprises a first transfer gate provided between said first node and second node and operated as a switch according to a transfer signal, a second transfer gate provided between said first node and third node and operated as a a switch in a complementary manner to said first transfer gate according to said transfer signal, a first switch element coupled to said second node and turning second node to a first fixed potential when said first transfer gate is kept off, and a second switch element coupled to said third node and turning said third node to a second fixed potential when said selection signal is supplied to said second node; a plurality of first memory cells selected according to the selection signal supplied to said second node through said line change-over circuit; and a plurality of second memory cells selected according to the selection signal supplied to said third node through said line change-over circuit.
Claim 8
Dependent Claim
190 words
A semiconductor memory, comprising; a first node to which a selection signal formed according to address signals is supplied; a line change-over circuit provided between said first node and second and third nodes, which comprises a first transfer gate provided between said first node and second node and operated as a switch according to a transfer signal, a second transfer gate provided between said first node and third node and operated as a a switch in a complementary manner to said first transfer gate according to said transfer signal, a first switch element coupled to said second node and turning second node to a first fixed potential when said first transfer gate is kept off, and a second switch element coupled to said third node and turning said third node to a second fixed potential when said selection signal is supplied to said second node; a plurality of first memory cells selected according to the selection signal supplied to said second node through said line change-over circuit; and a plurality of second memory cells selected according to the selection signal supplied to said third node through said line change-over circuit.
Claim 9
Dependent Claim
32 words
A semiconductor memory as defined in claim 6, wherein said first and second fixed potentials are kept at a level of which said first and second memory cells are not selected respectively.
Claim 10
Dependent Claim
41 words
A semiconductor memory as defined in claim 7, said line change-over circuit wherein said second switch element coupled to said third node and turning said third node to the second fixed potential operated as a switch according to said selection signal.
Claim 11
Dependent Claim
38 words
A semiconductor memory as defined in claim 7, further comprising a retaining circuit coupled to said third node and giving a positive feedback signal to said third node by referring to a signal level of said third node.
Claim 12
Dependent Claim
20 words
A semiconductor memory as defined in claim 7, each said first and second memory cells comprising a static memory cell.
Claim 13
Dependent Claim
218 words
A semiconductor memory, comprising a plurality of first nodes, each of which is supplied with a selection signal formed according to an address signal; a plurality of second nodes corresponding respectively to said first nodes; a third node; a plurality of line change-over circuits respectively provided between the first nodes and the second nodes corresponding to each other, each of which line change-over circuits comprises a first transfer gate provided between the first node corresponding thereto and the second node and operating as a switch according to a transfer signal, a second transfer gate provided between the first node corresponding thereto and said third node and operating as a switch in a complementary manner to said first transfer gate according to said transfer signal, a first switch element coupled to said first node corresponding thereto and turning said second node to a first fixed potential when said first transfer gate is kept off, and a second switch element coupled to said third node and turning said third node to a second fixed potential when a selection signal is supplied to said second node corresponding thereto; a plurality of first memory cells selected on said selection signal supplied to the second nodes; and a plurality of second memory cells selected on said selection signal supplied to the third node.
Claim 14
Dependent Claim
218 words
A semiconductor memory, comprising a plurality of first nodes, each of which is supplied with a selection signal formed according to an address signal; a plurality of second nodes corresponding respectively to said first nodes; a third node; a plurality of line change-over circuits respectively provided between the first nodes and the second nodes corresponding to each other, each of which line change-over circuits comprises a first transfer gate provided between the first node corresponding thereto and the second node and operating as a switch according to a transfer signal, a second transfer gate provided between the first node corresponding thereto and said third node and operating as a switch in a complementary manner to said first transfer gate according to said transfer signal, a first switch element coupled to said first node corresponding thereto and turning said second node to a first fixed potential when said first transfer gate is kept off, and a second switch element coupled to said third node and turning said third node to a second fixed potential when a selection signal is supplied to said second node corresponding thereto; a plurality of first memory cells selected on said selection signal supplied to the second nodes; and a plurality of second memory cells selected on said selection signal supplied to the third node.
Claim 15
Dependent Claim
28 words
A semiconductor memory as defined in claim 11, wherein said first and second memory cells are constituted each of a memory cell capable of writing and reading data.
Claim 16
Dependent Claim
43 words
A semiconductor memory as defined in claim 12, further comprising a plurality of state setting circuits provided one-to-one to each line change-over circuit, each state setting circuit including a program element for determining a level of the transfer signal to be outputted therefrom.
Claim 17
Dependent Claim
23 words
A semiconductor memory as defined in claim 13, said program element comprising a resistance element lowered in resistance by execution of a program.
Claim 18
Dependent Claim
15 words
A semiconductor memory as defined in claim 13, said program element comprising a fuse element.
Claim 19
Dependent Claim
113 words
A semiconductor memory as defined in claim 13, further comprising: a plurality of first data lines to which data input/output terminals of said first memory cells are coupled; a second data line to which data input/output terminals of said second memory cells are coupled; a common data line; a plurality of first column switches provided between said first data lines and said common data line and operating as a switch according to a selection signal supplied to the second nodes corresponding thereto; and a second column switch provided between said second data line and said common data line and operating as a switch according to a selection signal supplied to said third node.
References Cited (Backward Citations)
US4434479A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |