US4641172A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buried PN junction isolation regions for high power semiconductor devices
Assignee: Mitsubishi Electric Corp
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Filing: 1982-08-26
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Granted: 1987-02-03
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Expires: 2002-08-26
Abstract
Abstract A P type buried layer which is buried in an N type low resistance substrate is formed directly through a diffusion after which an N type buried layer is formed through a diffusion. Thereafter, an N type high resistance layer is epitaxially grown on the entire area of the upper surface thereof.
Inventors
- 👤 Shiro Iwatani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:44
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/641; H10D84/642; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
126 words
A semiconductor device having a plurality of circuit elements comrpising: a first substrate layer of a first conductivity type and a low resistance; a second substrate layer of said first conductivity type and a high resistance containing at least one of said plurality of circuit elements; a region of said first conductivity type and a high resistance containing at least one of said plurality of circuit elements, said region being isolated from said first and second substrate layers by an enclosed wall comprising a buried portion of a second conductivity type arranged so as to bridge said first and second substrate layers and another portion contiguous with said buried portion and of said second conductivity type, said another portion being wholly within said second substrate layer.
Claim 2
Dependent Claim
126 words
A semiconductor device having a plurality of circuit elements comrpising: a first substrate layer of a first conductivity type and a low resistance; a second substrate layer of said first conductivity type and a high resistance containing at least one of said plurality of circuit elements; a region of said first conductivity type and a high resistance containing at least one of said plurality of circuit elements, said region being isolated from said first and second substrate layers by an enclosed wall comprising a buried portion of a second conductivity type arranged so as to bridge said first and second substrate layers and another portion contiguous with said buried portion and of said second conductivity type, said another portion being wholly within said second substrate layer.
Claim 3
Dependent Claim
59 words
A semiconductor device as recited in claim 1, wherein said plurality of circuit elements comprises at least one high power semiconductor element and control circuit elements; and wherein said high power element is formed wholly within said second substrate layer and said control circuit elements are formed wholly within said isolated high resistance region of said first conductivity type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |