Method of manufacturing semiconductor devices utilizing epitaxial deposition and triple diffusion

Claim 1

A method of manufacturing a semiconductor device having at least one power transistor and a plurality of transistors for small signals formed on one semiconductor substrate, comprising the steps of: preparing a highly doped semiconductor substrate of one conductivity type, providing a semiconductor layer of said one conductivity type on an entire surface of said substrate, said semiconductor layer having a high specific resistance, simultaneously providing at least a first and a second highly doped semiconductor regions of the other conductivity type in and around the surface portion of said semiconductor layer, said first region serving as a base region for said power transistor and said second region forming separation regions for said plurality of transistors for small signals, providing a highly doped, third semiconductor region of said one conductivity type in said first highly doped semiconductor region of said other conductivity type and simultaneously providing a plurality of highly doped, fourth semiconductor regions of said one conductivity type in said second semiconductor region, providing a highly doped, fifth semiconductor regions of said other conductivity type in each of said fourth semiconductor regions simultaneously, simultaneously providing a highly doped, sixth semiconductor regions of said one conductivity type in each of said fifth semiconductor regions, and providing electrodes on said substrate, said first region, said third region, said fourth regions, said fifth regions and said sixth regions, respectively.

Claim 2

A method of manufacturing a semiconductor device having at least one power transistor and a plurality of transistors for small signals formed on one semiconductor substrate, comprising the steps of: preparing a highly doped semiconductor substrate of one conductivity type, providing a semiconductor layer of said one conductivity type on an entire surface of said substrate, said semiconductor layer having a high specific resistance, simultaneously providing at least a first and a second highly doped semiconductor regions of the other conductivity type in and around the surface portion of said semiconductor layer, said first region serving as a base region for said power transistor and said second region forming separation regions for said plurality of transistors for small signals, providing a highly doped, third semiconductor region of said one conductivity type in said first highly doped semiconductor region of said other conductivity type and simultaneously providing a plurality of highly doped, fourth semiconductor regions of said one conductivity type in said second semiconductor region, providing a highly doped, fifth semiconductor regions of said other conductivity type in each of said fourth semiconductor regions simultaneously, simultaneously providing a highly doped, sixth semiconductor regions of said one conductivity type in each of said fifth semiconductor regions, and providing electrodes on said substrate, said first region, said third region, said fourth regions, said fifth regions and said sixth regions, respectively.

Claim 8

A method of manufacturing a semiconductor device as in claims 1 or 6 wherein said fourth region, said fifth regions and said sixth regions define, collector and base, and emitter regions respectively for said small signal transistors.