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US4640000A
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US
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Method of manufacturing semiconductor device
Assignee: Toshiba Corp
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Filing: 1984-12-26
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Granted: 1987-02-03
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Expires: 2004-12-26
Abstract
Abstract A semiconductor device is fabricated by forming a gate structure including a gate insulating film and a gate electrode film formed thereon on a surface of an element formation region defined in a surface of a semiconductor substrate by an element isolation region. Then, an impurity having a conductivity type opposite to that of the substrate is doped by using the gate structure as a mask, thereby forming first and second semiconductor regions in the element formation region. An insulating wall is formed on a side wall of the gate structure, and an insulating film is deposited on an entire surface of the resultant semiconductor substrate structure. A portion of the insulating film which corresponds to a step portion formed by surfaces of the wall and the element formation region is selectively etched to form first and second contact holes. Finally, a wiring layer is formed on the remaining insulating film so as to electrically connect to the first and second semiconductor regions through the first and second contact holes.
Inventors
- 👤 Masaki Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
219 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an element isolation region in a surface of a semiconductor substrate of a first conductivity type to provide an island element region surrounded by said element isolation region; forming a gate structure on a surface of said island element region, said gate structure including a gate insulating film and a gate electrode film formed thereon; doping an impurity having a second conductivity type opposite to the first conductivity type by using said gate structure as a mask, thereby forming first and second semiconductor regions in the island element region; forming a wall of an insulating material on a side wall of said gate structure; depositing an insulating film on an entire surface of said semiconductor substrate which includes said element isolation region, said island element region and said gate structure including said wall; selectively etching a portion of said insulating film which corresponds to a step portion formed by surfaces of said insulating wall and said island element region to form first and second contact holes so as to partially expose said first and second semiconductor regions therethrough; and forming a wiring layer on the remaining insulating film so as to electrically connect to said first and second semiconductor regions through said first and second contact holes.
Claim 2
Independent Claim
219 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an element isolation region in a surface of a semiconductor substrate of a first conductivity type to provide an island element region surrounded by said element isolation region; forming a gate structure on a surface of said island element region, said gate structure including a gate insulating film and a gate electrode film formed thereon; doping an impurity having a second conductivity type opposite to the first conductivity type by using said gate structure as a mask, thereby forming first and second semiconductor regions in the island element region; forming a wall of an insulating material on a side wall of said gate structure; depositing an insulating film on an entire surface of said semiconductor substrate which includes said element isolation region, said island element region and said gate structure including said wall; selectively etching a portion of said insulating film which corresponds to a step portion formed by surfaces of said insulating wall and said island element region to form first and second contact holes so as to partially expose said first and second semiconductor regions therethrough; and forming a wiring layer on the remaining insulating film so as to electrically connect to said first and second semiconductor regions through said first and second contact holes.
Claim 3
Dependent Claim
56 words
A method according to claim 1, wherein said wall is formed by forming an insulating material layer on the entire surface of said semiconductor substrate, which includes said gate structure, said island element region and said element isolation region, and anisotropically etching said insulating material layer until an upper surface of said gate structure is exposed.
Claim 4
Dependent Claim
82 words
A method according to claim 1, wherein said wall is formed by forming an insulating material layer on the entire surface of said semiconductor substrate, which includes said gate structure, said island element region and said element isolation region, ion-implanting an impurity in a portion of said insulating material layer excluding a portion thereof which is formed on the side wall of said gate structure, and isotropically etching said insulating material layer to remove only the portion thereof doped with said impurity.
Claim 5
Dependent Claim
38 words
A method according to claim 1, wherein said insulating film is formed under a condition wherein the insulating film, which has a higher etching rate at a step portion thereof than at a flat portion thereof, is formed.
Claim 6
Dependent Claim
16 words
A method according to claim 4, wherein said insulating film comprises silicon oxide or silicon nitride.
Claim 7
Dependent Claim
17 words
A method according to claim 4, wherein said insulating film is formed by plasma chemical vapor deposition.
Claim 8
Dependent Claim
16 words
A method according to claim 4, wherein said insulating film is selectively etched by wet etching.
Claim 9
Dependent Claim
14 words
A method according to claim 4, wherein said insulating film is formed by sputtering.
Claim 10
Dependent Claim
52 words
The method of claim 1, further comprising forming a source region and a drain region by impurity doping in the first semiconductor region and forming a source region and drain region by impurity doping in the second semiconductor region prior to depositing an insulating film on the surface of the semiconductor substrate.
Claim 11
Dependent Claim
19 words
The method of claim 1, further comprising doping the gate structure with an impurity of the second conductivity type.
Claim 12
Dependent Claim
28 words
A method according to claim 1, further comprising the step of forming an insulating protective film between the upper surface of said gate structure and said insulating film.
Claim 13
Dependent Claim
13 words
A method according to claim 11, wherein said protective film comprises silicon oxide.
Claim 14
Dependent Claim
36 words
A method according to claim 11, wherein said protective film comprises a silicon oxide film directly formed on the upper surface of said gate structure and a silicon nitride film formed on said silicon oxide film.
Claim 15
Dependent Claim
23 words
A method according to claim 1, further comprising the step of forming a conductive material layer in said first and second contact holes.
Claim 16
Dependent Claim
24 words
A method according to claim 14, wherein said conductive material film is deposited by selective growth based on a reduction reaction of tungsten hexafluoride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |