Bit-line pull-up circuit

Claim 1

In a memory array, a circuit for establishing a given potential on the bit lines of the memory array comprising: first and second bit-lines for the application of complementary signals thereto; a relatively high impedance, low power dissipation, static circuit coupled to said bit-lines tending to maintain the potential on said bit-lines at a first given potential, said relatively high impedance circuit comprising: (a) a high impedance current limiting element having its conduction path connected between a point of operating potential and a first node; (b) first and second diode-connected transistors having their conduction paths connected between said first node and said first and second bit lines, respectively; and (c) said high impedance current limitigg element functioning to limit the voltage drop across said first and second diodes and maintaining the current therethrough a linear function of the applied voltage when either one of said first and second bit lines is short-circuited to a second potential; and a pulsed precharge circuit coupled to said bit lines for momentarily precharging said bit-lines to said first given potential prior to a read or a write cycle, said precharge circuit having a much lower impedance than said static circuit for driving said bit lines to said first given potential quickly.