Data transferring method

Claim 2

A high speed memory data transfer method for a word-organized memory arranged by rows and columns and having for each row N columns and P bits per word, said method comprising the steps of: (a) selecting a first row of said memory having data to be transferred to a second row of said memory, said second row being different from said first row; (b) transferring all N×P bits in said first row of memory to a set of P registers each having N words; (c) selecting said second row of said memory to receive said transferred data; and (d) transferring the contents of all said P registers to said second row of said memory.

Claim 3

The method of claim 1 wherein said transferring steps each include the step of effecting a parallel data transfer.

Claim 4

The method of claim 1 wherein said selecting steps each include the step of enabling a row decoder of said memory with selected portion of an address for said memory.

Claim 5

The method of claim 1 wherein said first transferring step includes the step of sending a read signal to said memory and wherein said second transferring step includes the step of sending a write signal to said memory.

Claim 8

The method of claim 5 wherein said set of P registers of N words includes first and second P register sets of N words per register and wherein said method further includes the step of transferring the contents of said first register set to said second register set.

Claim 10

The methods of claims 5 or 6 wherein said selecting steps each include the step of enabling a row detector with selected portions of an address for said memory.

Claim 11

The methods of claims 5 or 6 wherein said step of transferring data from said first memory includes the step of sending a read signal to said first memory and wherein said step of transferring data to said second memory includes the step of sending a write signal to said second memory.

Claim 12

A memory addressed by an address word comprising: a word-organized memory cell assembly arranged as M rows by N words with P bits per word; a row decoder coupled to said memory cell assembly and enabled by certain bits of said address word; P registers of N words, coupled to said memory cell assembly to receive the data from an entire row of said memory selected by said row decoder and to present for input the data in an entire row of said memory selected by said row decoder; and P column decoders enabled by certain bits of said address word for transferring P-bit data between said P registers and a P-bit data bus.

Claim 13

A memory addressed by an address word comprising: a word-organized memory cell assembly arranged as M rows by N words with P bits per word; a row decoder coupled to said memory cell assembly and enabled by certain bits of said address word; P registers of N words, coupled to said memory cell assembly to receive the data from an entire row of said memory selected by said row decoder and to present for input the data in an entire row of said memory selected by said row decoder; and P column decoders enabled by certain bits of said address word for transferring P-bit data between said P registers and a P-bit data bus.

Claim 14

A memory arrangement comprising: (a) a first memory addressed by a first address word said first memory including; (i) a first word-organized memory cell assembly arranged as M rows by N columns with P bits per word, and (ii) a first row decoder coupled to said first memory cell assembly and enabled by certain bits of said first address word; (b) a second memory addressed by a second address word, said second memory including (i) a second word-organized memory cell assembly arranged as M' rows by N columns and P bits per word, and (ii) a second row decoder coupled to said second memory cell assembly and enabled by certain bits of said second address word; and (c) P registers of N words coupled to said first memory cell assembly to receive an entire row of said first memory selected by said first row decoder and to present for input to said second memory an entire row selected by said second row decoder; and (d) P column decoders enabled by certain bits of said second address word for transferring P-bit data between said P registers and a P-bit data bus.

Claim 15

A memory arrangement comprising: (a) a first memory addressed by a first address word said first memory including; (i) a first word-organized memory cell assembly arranged as M rows by N columns with P bits per word, and (ii) a first row decoder coupled to said first memory cell assembly and enabled by certain bits of said first address word; (b) a second memory addressed by a second address word, said second memory including (i) a second word-organized memory cell assembly arranged as M' rows by N columns and P bits per word, and (ii) a second row decoder coupled to said second memory cell assembly and enabled by certain bits of said second address word; and (c) P registers of N words coupled to said first memory cell assembly to receive an entire row of said first memory selected by said first row decoder and to present for input to said second memory an entire row selected by said second row decoder; and (d) P column decoders enabled by certain bits of said second address word for transferring P-bit data between said P registers and a P-bit data bus.

Claim 16

A memory arrangement comprising: (a) a first memory addressed by a first address word, said first memory including (i) a first word-organized memory cell assembly arranged as M rows by N columns with P bits per word, (ii) a first row decoder coupled to said first memory cell assembly and enabled by certain bits of said first address word, and (iii) a first set of P registers of N words coupled to said first memory cell assembly to transfer an entire row of said first memory selected by said first row decoder; and (b) a second memory addressed by a second address word, said second memory including (i) a second word-organized memory cell assembly arranged as M' rows by N columns with P bits per word, (ii) a second row decoder coupled to said second memory cell assembly and enabled by certain bits of said second address word, (iii) a second set of P registers of N words coupled to said second memory cell assembly to transfer an entire row of said second memory selected by said second row decoder and coupled to transfer data with said first P register set; and (c) P column decoders enabled by certain bits of said second address word for transfering P-bit data between said second set of P registers and a P-bit data bus.

Claim 17

A memory arrangement comprising: (a) a first memory addressed by a first address word, said first memory including (i) a first word-organized memory cell assembly arranged as M rows by N columns with P bits per word, (ii) a first row decoder coupled to said first memory cell assembly and enabled by certain bits of said first address word, and (iii) a first set of P registers of N words coupled to said first memory cell assembly to transfer an entire row of said first memory selected by said first row decoder; and (b) a second memory addressed by a second address word, said second memory including (i) a second word-organized memory cell assembly arranged as M' rows by N columns with P bits per word, (ii) a second row decoder coupled to said second memory cell assembly and enabled by certain bits of said second address word, (iii) a second set of P registers of N words coupled to said second memory cell assembly to transfer an entire row of said second memory selected by said second row decoder and coupled to transfer data with said first P register set; and (c) P column decoders enabled by certain bits of said second address word for transfering P-bit data between said second set of P registers and a P-bit data bus.