US4354256A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1980-04-30
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Granted: 1982-10-12
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Expires: 2000-04-30
Abstract
Abstract A semiconductor memory device, comprising N memory cell arrays each of which includes a plurality of memory cells, is arranged to enable the use of said semiconductor memory device in the form of both one-bit-per-word N-bits-per-word. Two separate sets of output gates are provided, together with an additional input line for selecting between the two sets of gates. One set of gates is connected to provide one-bit output, and the other set of gates is connected to provide N-bit output.
Inventors
- 👤 Kiyoshi Miyasaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
268 words
A semiconductor memory device comprising: N memory cell arrays, each of said arrays including a plurality of memory cells, a plurality of address lines for selectively addressing individual memory cells of said arrays, a group of output gates of a first kind respectively corresponding to said memory cell arrays and operable when selectively enabled for simultaneously producing in parallel a corresponding plurality of 1-bit output signals selected from said respective N memory cell arrays by said address lines, a gate of a second kind common to all of said memory cell arrays and operable when selectively enabled for producing a particular 1-bit output signal selected from said N memory cell arrays by said address lines, a first decoder circuit for simultaneously enabling said output gates of said first kind, N other decoder circuits for enabling said gate of said second kind, a power supply terminal and a ground terminal, means for selectively applying relatively higher and lower potentials to said power supply terminal, said first decoder circuit and said N other decoder circuits respectively including means connected to said power supply terminal and responsive to said relatively higher and lower potentials thereof, selectively, for enabling said group of output gates of said first kind and disabling said gate of said second kind, and for disabling said output gates of said first kind and enabling said output gate of said second kind, said N memory cell arrays, said output gates of said first and said second kinds, said first decoder circuit, said N other decoder circuits, and said selective potential applying means being formed on a common semiconductor substrate.
Claim 2
Dependent Claim
268 words
A semiconductor memory device comprising: N memory cell arrays, each of said arrays including a plurality of memory cells, a plurality of address lines for selectively addressing individual memory cells of said arrays, a group of output gates of a first kind respectively corresponding to said memory cell arrays and operable when selectively enabled for simultaneously producing in parallel a corresponding plurality of 1-bit output signals selected from said respective N memory cell arrays by said address lines, a gate of a second kind common to all of said memory cell arrays and operable when selectively enabled for producing a particular 1-bit output signal selected from said N memory cell arrays by said address lines, a first decoder circuit for simultaneously enabling said output gates of said first kind, N other decoder circuits for enabling said gate of said second kind, a power supply terminal and a ground terminal, means for selectively applying relatively higher and lower potentials to said power supply terminal, said first decoder circuit and said N other decoder circuits respectively including means connected to said power supply terminal and responsive to said relatively higher and lower potentials thereof, selectively, for enabling said group of output gates of said first kind and disabling said gate of said second kind, and for disabling said output gates of said first kind and enabling said output gate of said second kind, said N memory cell arrays, said output gates of said first and said second kinds, said first decoder circuit, said N other decoder circuits, and said selective potential applying means being formed on a common semiconductor substrate.
Claim 3
Dependent Claim
56 words
A semiconductor memory device as defined in claim 1, mounted in a package having positive and negative power line connections, wherein said selective potential applying means comprises means for selectively connecting said power supply terminal to either said positive power line connection or said negative power line connection of said package of said semiconductor memory device.
Claim 4
Dependent Claim
28 words
A semiconductor memory device as defined in claim 2, wherein said selective connection means is formed by a wire-bonding process during the manufacture of the semiconductor memory device.
Claim 5
Dependent Claim
42 words
A semiconductor memory device as defined in claim 1, wherein said first decoder circuit comprises a plurality of first decoder transistors connected in parallel, each of said first decoder transistors comprising a gate which is connected to one of said address lines.
Claim 6
Dependent Claim
47 words
A semiconductor memory device as defined in claim 1, 3 or 4 wherein each of said second decoder circuits comprises a plurality of second decoder transistors connected in parallel, each of said second decoder transistors comprising a gate which is connected to one of said address lines.
Claim 7
Dependent Claim
28 words
A semiconductor memory device as defined in claim 5, wherein the number of said plurality of first decoder transistors is equal to the number of said address lines.
Claim 8
Dependent Claim
37 words
A semiconductor memory device as defined in claim 6, wherein the number of said plurality of second decoder transistors in each of said second decoder circuits is equal to one-half of the number of said address lines.
Claim 9
Dependent Claim
47 words
A semiconductor memory device as defined in claim 7, further comprising N cross-coupled latches, and wherein said first decoder circuit provides an output which causes each of said output gates of the first kind to connect one of said memory cell arrays with one of said latches.
Claim 10
Dependent Claim
51 words
A semiconductor memory device as defined in claim 8, further comprising an additional cross-coupled latch, and wherein each of said second decoder circuits causes said output gate of the second kind to connect said additional latch with a particular one of said N arrays which is selected by said address lines.
Claim 11
Dependent Claim
94 words
A semiconductor conductor memory device as defined in claim 1, wherein: said means of said first decoder circuit connected to said power supply terminal comprises a transistor connected between the output of said first decoder circuit and ground with the gate thereof connected to said power supply terminal, said means of said N other decoder circuits connected to said power supply terminal comprise respective, N second transistors having the drains thereof connected to said power supply terminal and connected to said respective N decoder circuits for supplying power thereto from said power supply terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-11 | 1986-04-12 | 1986-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-11 | 1990-04-12 | 1990-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-11 | 1994-04-12 | 1994-10-12 | $7700.00 | Window Closed / Lapsed |