Abstract A shift register-decoder circuit is adapted to preset the memory location in the data storage section of a permanent storage memory from which data is initially transferred to an output node. That circuit comprises a shift register having a plurality of stages and a corresponding plurality of logic decoder circuits. The logic decoder stages are operatively associated respectively with a plurality of column output nodes and are adapted in response to an input address signal to initially uniquely charge a selected one of said column output nodes. Subsequently, the logic decoder circuit is disabled and the shift register is enabled and is effective to shift the column select signal sequentially to successive columns under the influence of an external clock signal. The resulting data scanning operation continues until the memory is disabled by the operation of a disabling circuit.
A shift register circuit comprising a plurality of shift register stages each operably connected to a source of timed signals, a plurality of logic stages each having a logic terminal and receiving a set of input sIgnals different from said timed signals which are effective to establish a unique condition at one of said logic stages and to establish a unique signal level at a corresponding one of said logic terminals, a plurality of nodes, means actuatable by an enabling signal and effective when actuated to respectively operatively connect each of said logic terminals to said nodes thereby to establish a unique logic level at one of said nodes so connected to said one of said logic terminals, and effective in the subsequent absence of said enabling signal to disconnect said logic terminals from said nodes and to operatively connect said register stages to said nodes and thereafter to sequentially transfer said unique logic level from said one of said nodes to a succeeding one of said nodes during subsequent one of said timed signals.
Claim 2
Dependent Claim
175 words
A shift register circuit comprising a plurality of shift register stages each operably connected to a source of timed signals, a plurality of logic stages each having a logic terminal and receiving a set of input sIgnals different from said timed signals which are effective to establish a unique condition at one of said logic stages and to establish a unique signal level at a corresponding one of said logic terminals, a plurality of nodes, means actuatable by an enabling signal and effective when actuated to respectively operatively connect each of said logic terminals to said nodes thereby to establish a unique logic level at one of said nodes so connected to said one of said logic terminals, and effective in the subsequent absence of said enabling signal to disconnect said logic terminals from said nodes and to operatively connect said register stages to said nodes and thereafter to sequentially transfer said unique logic level from said one of said nodes to a succeeding one of said nodes during subsequent one of said timed signals.
Claim 3
Dependent Claim
78 words
The shift register of claim 1, in which said enabling signal is present only during a predetermined number of said timed signals, said connecting means comprising first switch means operatively connected between said logic terminals and said nodes receiving and actuated by said enabling signal, and second switch means operatively connected between said register stages and said nodes receiving the complement of said enabling signal so as to be actuated thereby when said enabling signal is not present.