Patent US4639845A successfully refreshed from Google Patents.
US4639845A
Expired / Lapsed
US
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Voltage inverter
Assignee: GTO ELECTRONICS A CORP OF
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Filing: 1984-05-11
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Granted: 1987-01-27
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Expires: 2004-05-11
Abstract
Abstract A voltage inverter is disclosed. A clock circuit provides timing signals to the electronics of the system. Electronics include a circuit for controlling the phase relationship between a pair of square waves, an overcurrent protection circuit, an auto-on circuit, a low voltage shutdown circuit, and output driver transistors for driving a primary transformer. A power transformer is connected to the primary transformer, and the output of the inverter is taken from the secondary transformer. Voltage and current magnitude indicative feedback signals are provided from the output of the inverter with the voltage signal being monitored by the phase varying circuit and the current feedback signal being monitored by the overcurrent protection circuit. Control of the off-time between alternating pulses during a cycle of the output is controlled by overlapping the square waves controlling the driver transistors for exitation of the primary transformer.
Inventors
- 👤 Eric G. Persson
- 👤 Ronald D. Veith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:39
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5383; H02M7/53846
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
224 words
A voltage inverter comprising: clocking means for producing a clock signal; output drive transistors for switching DC voltage in response to first and second drive signals; primary output transformer means connected to said output drive transistors for commutation of said switched DC voltage through said transformer; power output transformer means controlled by said primary transformer means for commutating of DC power through to an inverter output to produce an AC voltage; voltage sensing means connected to said power output transformer means for producing a first feedback signal indicative of the magnitude of the AC voltage output; pulse modulation means receiving said clock signal and said first feedback signal and operative in response thereto for producing first and second square wave control signals, the phase relationship between said control signals being varied according to the magnitude of the AC voltage output; and gating circuit means receiving said first and second square wave control signals for producing said first and second drive signals such that the first drive signal always has a greater active duty cycle than the second drive signal, causing said output drive transistors to be simultaneously active for the period of overlap between the active duty cycles of said first and second drive signals whereby the magnetic field in said primary output transformer is dynamically switched suppressing voltage spikes on said inverter output.
Claim 2
Dependent Claim
224 words
A voltage inverter comprising: clocking means for producing a clock signal; output drive transistors for switching DC voltage in response to first and second drive signals; primary output transformer means connected to said output drive transistors for commutation of said switched DC voltage through said transformer; power output transformer means controlled by said primary transformer means for commutating of DC power through to an inverter output to produce an AC voltage; voltage sensing means connected to said power output transformer means for producing a first feedback signal indicative of the magnitude of the AC voltage output; pulse modulation means receiving said clock signal and said first feedback signal and operative in response thereto for producing first and second square wave control signals, the phase relationship between said control signals being varied according to the magnitude of the AC voltage output; and gating circuit means receiving said first and second square wave control signals for producing said first and second drive signals such that the first drive signal always has a greater active duty cycle than the second drive signal, causing said output drive transistors to be simultaneously active for the period of overlap between the active duty cycles of said first and second drive signals whereby the magnetic field in said primary output transformer is dynamically switched suppressing voltage spikes on said inverter output.
Claim 3
Dependent Claim
60 words
A voltage inverter according to claim 1 further including auto-on means for sensing current demand in said power output transformer means and operable in response thereto for controlling the application of said first and second square wave signals to said gating circuit means such that the commutation of voltage through said transformers may be suspended when no demand is present.
Claim 4
Dependent Claim
48 words
A voltage inverter according to claim 2 further including a low voltage shutdown circuit responsive to low DC voltage supply levels and operably connected to said auto-on means to cause said auto-on means to suspend application of said first and second square waves to said gating circuit means.
Claim 5
Dependent Claim
60 words
A voltage inverter according to claim 2 further including overcurrent protection means for sensing current draw through the power output transformer, for monitoring said first feedback signal and operable in response thereto for causing said auto-on circuit to suspend application of said first and second square waves to gating circuit means when the threshold maximum output power level is passed.
Claim 6
Dependent Claim
47 words
A voltage inverter according to claim 1 wherein said output drive transistors comprises a pair of transistors and said primary output transformer means includes a centertapped primary winding, wherein each of said transistors control one half of the commutation of voltage through said primary output transformer means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |