Switching regulator

Claim 2

In a switching regulator including a DC voltage source having first and second DC output terminals; a switching transformer having a magnetic core, first and second primary windings connected in series, a secondary winding, a first switching transistor connected in series between said first and second DC output terminals through said first primary winding; a second switching transistor connected in series between said first and second DC output terminals through said first and second primary windings; rectifying means connected across said secondary winding, a load connected to said rectifying means; a clock pulse oscillator; a pulse width modulator supplied with both the outputs from said clock pulse oscillator and as well as the output from said rectifying means so as to produce a PWM control signal the duty of which is proportional to the voltage of said rectifying means; and circuit means for selectively supplying said PWM control signal to said first and second switching transistors in response to the circumstance of said load; said switching regulator further comprising: (a) reference pulse signal generating means for producing a reference pulse signal having a standard pulse width; (b) comparing means for comparing the pulse width of said PWM control signal with that of said reference pulse signal and producing a switching signal indicative of the circumstance of said load in response to the comparison result therebetween; and (c) said circuit means including a gate circuit supplied with the PWM control signal from said pulse width modulator and the switching signal from said comparing means so as to supply the PWM control signal to one of said first and second switching transistors in response to said switching signal.

Claim 3

A switching regulator according to claim 1, further including memory means for memorizing said switching signal from said comparing means so as to continuously supply said switching signal to one of said first and second switching transistors during the same circumstance of said load.

Claim 4

A switching regulator according to claim 2, in which said memory means comprises a D-type flip-flop.

Claim 5

A switching regulator according to claim 3, in which said D-type flip-flop has a T-terminal connected to the output of said clock pulse oscillator, a D-terminal connected to the output of said comparing means and a pair of Q and Q output terminals connected to said gate circuit means, respectively.

Claim 6

A switching regulator according to claim 4, in which said gate circuit means comprises a pair of AND gate circuits each having a pair of input terminals and an output terminal, one of said input terminals of the pair of AND gate circuits being connected to the Q and Q output terminals of said D-type flip-flop, respectively, the other of said input terminals of said pair of AND gate circuits being connected to the output of said pulse width modulator, and said output terminals of said pair of AND gate circuits being connected to said first and second switching transistors, respectively.

Claim 7

In a switching regulator including a DC voltage source having a pair of first and second DC output terminals; a switching transformer having a magnetic core, first and second primary windings connected in series, a secondary winding; a first switching transistor connected in series between said first and second DC output terminals through said first primary winding; a second switching transistor connected in series between said first and second DC output terminals through said first and second primary windings; rectifying means connected across said secondary winding; a load connected to said rectifying means; a clock pulse oscillator; a pulse width modulator supplied with outputs from both said clock pulse oscillator and said rectifying means so as to produce PWM control signal the duty of which is proportional to the voltage of said rectifying means; and circuit means for selectively supplying said PWM control signal to said first and second switching transistors in response to the circumstance of said load; said switching regulator further comprising: (a) first reference pulse signal generating means for producing a first reference pulse signal having a first standard pulse width; (b) second reference pulse signal generating means for producing a second reference pulse signal having a second standard pulse width which is larger than that of said first standard pulse width; (c) reference pulse selective means for selecting one of said first and second reference pulse signals and producing the same at the output terminal thereof; (d) comparing means for comparing the pulse width of said PWM control signal with that of one of said first and second reference pulse signals and producing a switching signal indicative of the circumstance of said load in response to the comparison result therebetween; and (e) said circuit means including a gate circuit supplied with the PWM control signal from said pulse width modulator and said switching signal from said comparing means so as to supply the PWM control signal to one of said first and second switching transistors in response to the switching signal.

Claim 8

In a switching regulator including a DC voltage source having a pair of first and second DC output terminals; a switching transformer having a magnetic core, first and second primary windings connected in series, a secondary winding; a first switching transistor connected in series between said first and second DC output terminals through said first primary winding; a second switching transistor connected in series between said first and second DC output terminals through said first and second primary windings; rectifying means connected across said secondary winding; a load connected to said rectifying means; a clock pulse oscillator; a pulse width modulator supplied with outputs from both said clock pulse oscillator and said rectifying means so as to produce PWM control signal the duty of which is proportional to the voltage of said rectifying means; and circuit means for selectively supplying said PWM control signal to said first and second switching transistors in response to the circumstance of said load; said switching regulator further comprising: (a) first reference pulse signal generating means for producing a first reference pulse signal having a first standard pulse width; (b) second reference pulse signal generating means for producing a second reference pulse signal having a second standard pulse width which is larger than that of said first standard pulse width; (c) reference pulse selective means for selecting one of said first and second reference pulse signals and producing the same at the output terminal thereof; (d) comparing means for comparing the pulse width of said PWM control signal with that of one of said first and second reference pulse signals and producing a switching signal indicative of the circumstance of said load in response to the comparison result therebetween; and (e) said circuit means including a gate circuit supplied with the PWM control signal from said pulse width modulator and said switching signal from said comparing means so as to supply the PWM control signal to one of said first and second switching transistors in response to the switching signal.

Claim 9

A switching regulator according to claim 6, further including memory means for memorizing said switching signal from said comparing means so as to continuously supplying the switching signal to one of said first and second switching transistors during the same circumstance of said load.

Claim 10

A switching regulator according to claim 7, in which said memory means comprises a D-type flip-flop.

Claim 11

A switching regulator according to claim 8, in which said D-type flip-flop has a T-terminal connected to the output of said clock pulse oscillator, a D-terminal connected to the output of said comparing means and a pair of Q and Q terminals connected to said gate circuit means, respectively.

Claim 12

A switching regulator according to claim 9, in which said gate circuit means comprises a pair of AND gate circuits each having a pair of input terminals and an output terminal, one of said input terminals of said pair of AND gate circuits being connected to the Q and Q terminals of said D-type flip-flop, respectively, the other of input terminals of the pair of said AND gate circuits being connected to the output of said pulse width modulator, and output terminals of the pair of AND gate circuits being connected to said first and second switching transistors, respectively.

Claim 13

A switching regulator according to claim 10, which further includes an exclusive OR gate circuit having a pair of input terminals and an output terminal; one of the said of input terminals being connected to the output of said pulse width modulator, the other of said input terminals being connected to the Q-terminal of said D-type flip-flop and the output terminal being connected to said comparing means.