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US4635229A
Expired / Lapsed
US
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Semiconductor memory device including non-volatile transistor for storing data in a bistable circuit
Assignee: NEC Corp
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Filing: 1985-01-17
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Granted: 1987-01-06
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Expires: 2005-01-17
Abstract
Abstract A non-volatile random access memory device includes a plurality of memory cells, each of which has a bistable (flip-flop) circuit which acts as an ordinary random access memory cell and at least one non-volatile memory transistor. The bistable circuit has two output terminals (a true output terminal and a complementary output terminal). One of the two output terminals is coupled to a control electrode of the non-volatile memory transistor, and the other output terminal is coupled to the drain of the non-volatile memory transistor. The source of the non-volatile memory transistor is coupled to a driving voltage source (e.g. 5 V) via a switching gate which is turned on when a control signal is applied thereto. In a normal operation mode, a normal driving voltage (e.g. 5 V) is supplied to the bistable circuit. On the other hand, when data in the bistable circuit is to be sheltered in the non-volatile memory transistor, a high voltage (e.g. 20 V) is supplied to the bistable circuit, whereby the non-volatile memory transistor stores the data in the bistable circuit. When the data stored in the non-volatile memory transistor is to be returned to the bistable circuit, the switching gate is turned on in response to a control signal. Thus, the data in the non-volatile memory transistor is restored in the bistable circuit. These operations can be easily performed at high speed with simple hardware elements.
Inventors
- 👤 Koichiro Okumura
- 👤 Takeshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:46
CPC Classifications
G; G11; G11C; G11C14/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
228 words
A semiconductor memory device having a plurality of memory cells on a single semiconductor chip, each of said memory cells comprising; a bistable circuit coupled between a reference voltage source and a power supply terminal and having two output terminals, one of said two output terminals being coupled to a true digit line via a first transfer gate, and the other output terminal being coupled to a complementary digit line via a second transfer gate, means for selectively supplying a first voltage or a second voltage higher than said first voltage to said bistable circuit through said power supply terminal, a non-volatile memory transistor having a control electrode coupled to one of said two output terminals of said bistable circuit, and having one of a source and drain coupled to the other of said two output terminals of said bistable circuit, for selectively storing the contents of said bistable circuit, and switching means coupled to the other of said source and drain of said non-volatile memory transistor for applying a driving voltage thereto, and a power-on reset circuit provided on said semiconductor chip and generating a reset signal when power for driving the memory device is supplied to said semiconductor chip, said switching means being activated by said reset signal to apply a driving voltage at the other of said source and drain of said non-volatile memory transistor.
Claim 2
Dependent Claim
228 words
A semiconductor memory device having a plurality of memory cells on a single semiconductor chip, each of said memory cells comprising; a bistable circuit coupled between a reference voltage source and a power supply terminal and having two output terminals, one of said two output terminals being coupled to a true digit line via a first transfer gate, and the other output terminal being coupled to a complementary digit line via a second transfer gate, means for selectively supplying a first voltage or a second voltage higher than said first voltage to said bistable circuit through said power supply terminal, a non-volatile memory transistor having a control electrode coupled to one of said two output terminals of said bistable circuit, and having one of a source and drain coupled to the other of said two output terminals of said bistable circuit, for selectively storing the contents of said bistable circuit, and switching means coupled to the other of said source and drain of said non-volatile memory transistor for applying a driving voltage thereto, and a power-on reset circuit provided on said semiconductor chip and generating a reset signal when power for driving the memory device is supplied to said semiconductor chip, said switching means being activated by said reset signal to apply a driving voltage at the other of said source and drain of said non-volatile memory transistor.
Claim 3
Dependent Claim
67 words
A semiconductor memory device as claimed in claim 1, in which said first voltage is applied to said bistable circuit through said power supply terminal when said bistable circuit acts as an ordinary random access memory cell, while said second voltage is applied to said bistable circuit through said power supply terminal when data in said bistable circuit is to be sheltered in said non-volatile memory transistor.
Claim 4
Dependent Claim
183 words
A semiconductor device, comprising; a power-on reset circuit generating a reset signal whenever driving power is supplied to the semiconductor device, and at least one memory element, said memory element comprising a flip-flop circuit and a non-volatile transistor having a control electrode and two contact portions which act as a source region and a drain region, respectively, said control electrode of said non-volatile transistor being coupled to one output of said flip-flop circuit, one of said two contact portions of said non-volatile transistor being coupled to the other output of said flip-flop circuit, the other of said two contact portions receiving a driving voltage when data stored in said non-volatile transistor is to be written into said flip-flop circuit, and a switching transistor receiving said driving voltage at one terminal and being connected at another terminal to said non-volatile transistor, and being turned on in response to said reset signal generated by said power-on reset circuit; and said flip-flop circuit receiving a control voltage which can activate said non-volatile transistor when data in said flip-flop is to be stored in said non-volatile transistor.
Claim 5
Dependent Claim
183 words
A semiconductor device, comprising; a power-on reset circuit generating a reset signal whenever driving power is supplied to the semiconductor device, and at least one memory element, said memory element comprising a flip-flop circuit and a non-volatile transistor having a control electrode and two contact portions which act as a source region and a drain region, respectively, said control electrode of said non-volatile transistor being coupled to one output of said flip-flop circuit, one of said two contact portions of said non-volatile transistor being coupled to the other output of said flip-flop circuit, the other of said two contact portions receiving a driving voltage when data stored in said non-volatile transistor is to be written into said flip-flop circuit, and a switching transistor receiving said driving voltage at one terminal and being connected at another terminal to said non-volatile transistor, and being turned on in response to said reset signal generated by said power-on reset circuit; and said flip-flop circuit receiving a control voltage which can activate said non-volatile transistor when data in said flip-flop is to be stored in said non-volatile transistor.
Claim 6
Dependent Claim
49 words
A semiconductor device as claimed in claim 3, wherein said flip-flop circuit comprises two inverters of a complementary type, an input of one inverter being coupled to an output of the other inverter and an input of said other inverter being coupled to an output of said one inverter.
Claim 7
Dependent Claim
73 words
A semiconductor memory device as claimed in claim 1, wherein said non-volatile memory transistor comprises a dual gate device having a floating gate having at least one portion arranged proximate a drain region, and a control gate disposed above said floating gate, said non-volatile memory transistor performing a writing operation to store the contents of said bistable circuit upon the application of said second voltage across said control gate and said drain region.
Claim 8
Dependent Claim
41 words
A semiconductor memory device as claimed in claim 1, wherein said bistable circuit comprises a flip-flop circuit constituted of a pair of cross connected inverters, each of said inverters comprising a series connected depletion type IGFET and an enhancement type IGFET.
Claim 9
Dependent Claim
37 words
A semiconductor memory device as claimed in claim 6, wherein said bistable circuit comprises a flip-flop circuit constituted of a pair of cross-coupled inverters, each of said converters comprising a series connected P-channel MOSFET and N-channel MOSFET.
Claim 10
Dependent Claim
49 words
A semiconductor memory device as claimed in claim 1, wherein said means for selectively supplying comprises a select circuit disposed on said chip for selecting between a source of said first voltage and a source of said second voltage, both of said sources being located externally of said chip.
Claim 11
Dependent Claim
91 words
A semiconductor memory device as claimed in claim 1 further comprising means for generating said second voltage located on said chip, said second voltage generating means comprising a terminal for receiving said first voltage, a pair of serially connected transistors respectively receiving true and complemented control signals, a charging circuit connected between said transistors, a further transistor coupled between a source of said first voltage and an output of said charging circuit and receiving said true control signal, and an output terminal connected to said bistable circuits of said memory cells.
Claim 12
Dependent Claim
34 words
A semiconductor memory device as claimed in claim 9, wherein said charging circuit comprises a plurality of serially connected IGFETs having interconnected gates and drains, and a charging capacitor coupled to each said gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |