Data processor having selective breakpoint capability with minimal overhead

Claim 2

In a data processor adapted to communicate with a peripheral device, the data processor comprising: an instruction register for storing an instruction to be executed by said data processor; and instruction execution control means, for (1) executing instructions stored in the instruction register, and, in response to executing a breakpoint instruction, (2) providing a control signal to said peripheral device; (3) receiving a first response from said peripheral device and (4a) either performing a breakpoint, if the first response is of a first type; (4b) or sorting a successive instruction in the instruction register, if the first response is of a second type; the improvement wherein the instruction execution control means also receives a second response from said peripheral device, the instruction execution control means storing said second response in said instruction register as said successive instruction if said first response is of said second type.

Claim 5

A data processor having selective breakpoint capability with minimal overhead by communicating operands with a peripheral device, comprising: register means for storing instructions to be executed by the data processor; and control means for controlling the execution of the stored instructions in the register means, for directing the peripheral device to either send a control signal directing a breakpoint or send a successive instruction in response to executing a predetermined breakpoint instruction, for receiving and storing the successive instruction in the register means as a next instruction to be executed, and for executing the successive instruction.

Claim 6

A data processor having selective breakpoint capability with minimal overhead by communicating operands with a peripheral device, comprising: register means for storing instructions to be executed by the data processor; and control means for controlling the execution of the stored instructions in the register means, for directing the peripheral device to either send a control signal directing a breakpoint or send a successive instruction in response to executing a predetermined breakpoint instruction, for receiving and storing the successive instruction in the register means as a next instruction to be executed, and for executing the successive instruction.

Claim 7

A data processing system comprising the data processor and peripheral device of claim 1, the peripheral device being coupled to the data processing system via a data bus and comprising: decoder means having an input for receiving address signals from the data processor, a predetermined one of the address signals indicating a breakpoint instruction, and having a first output for providing a breakpoint acknowledge signal, a second output for providing an initialization signal, and a third output for providing a read/write control signal; counter means having a first input for receiving the breakpoint acknowledge signal, a second input for receiving the initialization signal, and an output for indicating when a predetermined count has been completed thereby selectively indicating when a breakpoint should be taken; a control circuit having a first input for receiving the breakpoint acknowledge signal, a second input for receiving the initialization signal, a third input coupled to the output of the counter means, a first output for providing the first type of first response, a second output for providing the second type of first response, and a third output for providing a data bus control signal; and buffer means having a first input for receiving the data bus control signal, a second input for receiving the read/write control signal, and an output for providing the second response.

Claim 8

The method of claim 2 further comprising the step of: reexecuting the breakpoint instruction a predetermined plurality of times before performing the breakpoint.