TTL buffer circuit incorporating active pull-down transistor

Claim 2

In a double inversion buffer incorporating a first circuit means to invert a digital input signal, a second circuit means to produce re-inversion of said digital input signal, and output stage means for receiving said twice inverted signal and providing an external output signal, including an output line, pull-up means and a pull-down transistor connected between said output line and ground, the improvement comprising: a transistor connected between the base of said pull-down transistor and ground to fully discharge said pull-down transistor in response to the operation of said first circuit means.

Claim 3

An improved double inversion buffer in accordance with claim 1 in combination with clamping circuit means connected to the output of said output stage to limit the output voltage level of said double inversion buffer to thereby decrease the low-to-high and high-to-low transition times of said signal on said output line.

Claim 4

An improved double inversion buffer in accordance with claim 1 wherein: said first circuit means comprises a first transistor whose base is connected to the input terminal of said double inversion buffer, whose emitter is connected through a resistor to a voltage supply line and whose collector is connected to ground, diode means connected between the base of said first transistor and the base of a second transistor, the collector of said second transistor being connected through a resistor to said voltage supply line, and a third transistor whose emitter is coupled to the base of said second transistor, whose base is connected to the emitter of said first transistor, and whose collector is connected through a resistor to said voltage supply line, the collector of said second transistor producing a signal which is an inverted representation of said digital input signal; said second circuit means comprises a fourth transistor whose base is connected to the emitter of said second transistor, whose collector is connected through a resistor to said voltage supply line, and through a diode to the collector of said second transistor, whose emitter is connected to ground, a fifth transistor whose base is coupled to the collector of said fourth transistor, whose collector is connected through a resistor to said voltage supply line and whose emitter is connected to the base of said pull-down transistor, and a sixth transistor whose base is connected to the collector of said fifth transistor, whose emitter is connected through a resistor to ground and whose collector is connected through a resistor to said voltage supply line; and said pull-up means comprises a pull-up transistor whose collector is cnnected through a resistor to said voltage supply line, whose base is connected to the emitter of said sixth transistor and whose emitter is connected to said output line; said pull-down transistor has its collector connected to said output line, and its emitter connected to ground; and said transistor means comprises a Schottky transistor whose collector is coupled to the emitter of said fifth transistor and to the base of said pull-down transistor, whose base is connected to the emitter of said second transistor, and whose emitter is connected to ground.

Claim 5

An improved double inversion buffer in accordance with claim 3 in combination with a clamping circuit connected to said output stage for limiting the voltage levels on said output and reducing the state transistion times.

Claim 6

An improved double inversion buffer in accordance with claim 4 where said clamping circuit comprises: a seventh transistor whose base is connected to the emitter of said pull-up transistor, whose emitter is connected through a diode string to ground, and whose collector is connected through a resistor to the voltage supply line and through a Schottky diode to the base of said sixth transistor.

Claim 7

An improved double inversion buffer in accordance with claim 5 wherein said diode string comprises series connected diodes having their anode side connected to the emitter of said seventh transistor.