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US4633571A
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Method of manufacturing a CMOS cell array with transistor isolation
Assignee: Nokia Bell Labs
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Filing: 1985-10-02
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Granted: 1987-01-06
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Expires: 2005-10-02
Abstract
Abstract A new technique for forming CMOS custom logic circuits is disclosed wherein standard cells (10,12,14) are used and the prior art technique of field oxide isolation (16) is replaced with transistor isolation (68-71). That is, the boundaries (18,20,22,24) between the cells are formed by transistors that are permanently "off", i.e., tied to the positive or negative voltage supply, depending on whether the transistors are p-channel or n-channel devices, respectively. Therefore, instead of having to deposit separate p+ and n+ source/drain diffusions for each cell, as in the prior art, a single p+ diffusion strip (60) and a single n+ diffusion strip (62) are utilized, where the polysilicon mask of both the logic and isolation transistors defines the cell sizes. Thus, the p+ and n+ diffusions become generic steps which do not vary from circuit to circuit, decreasing the turnaround time associated with custom logic circuit layout and design.
Inventors
- 👤 Kevin D. Kolwicz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:03
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10W; H10W10/00; H10W10/01; H10W10/051; H10W10/50
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
213 words
A method for producing a CMOS custom logic circuit including a plurality of cells separated from one another by a cell boundary, each cell including at least one complementary logic transistor pair, the method including the steps of (a) depositing a first, continuous thin oxide strip onto a substrate material; (b) depositing a second, continuous thin oxide strip onto said substrate material parallel to said first strip and separated therefrom by a predetermined distance; (c) implanting ions of a first conductivity type in said first, continuous thin oxide strip; (d) implanting ions of a second conductivity type in said second, continuous thin oxide strip; (e) growing a field oxide region on said substrate between said first and second continuous strips; (f) depositing a polysilicon patterned mask layer on said first and second continuous strips to form, in association with said first and second continuous strips, a plurality of transistors wherein selected sets from said plurality of transistors form logic transistors and are included in said plurality of cells, and selected others of said plurality of transistors form a plurality of isolation transistors and are permanently connected to either one of a positive voltage supply and a negative voltage supply for isolating said plurality of cells from one another and forming the cell boundaries.
Claim 2
Independent Claim
213 words
A method for producing a CMOS custom logic circuit including a plurality of cells separated from one another by a cell boundary, each cell including at least one complementary logic transistor pair, the method including the steps of (a) depositing a first, continuous thin oxide strip onto a substrate material; (b) depositing a second, continuous thin oxide strip onto said substrate material parallel to said first strip and separated therefrom by a predetermined distance; (c) implanting ions of a first conductivity type in said first, continuous thin oxide strip; (d) implanting ions of a second conductivity type in said second, continuous thin oxide strip; (e) growing a field oxide region on said substrate between said first and second continuous strips; (f) depositing a polysilicon patterned mask layer on said first and second continuous strips to form, in association with said first and second continuous strips, a plurality of transistors wherein selected sets from said plurality of transistors form logic transistors and are included in said plurality of cells, and selected others of said plurality of transistors form a plurality of isolation transistors and are permanently connected to either one of a positive voltage supply and a negative voltage supply for isolating said plurality of cells from one another and forming the cell boundaries.
Claim 3
Dependent Claim
60 words
The method according to claim 1 wherein the plurality of isolation transistors are formed in pairs, the first transistor of each pair disposed across the first continuous strip of the first conductivity type and the second transistor of each pair positioned in line with its associated first transistor and disposed over the second continuous strip of the second conductivity type.
Claim 4
Dependent Claim
28 words
The method according to claim 1 wherein the first continuous strip comprises a p+ type diffusion layer and the second continuous strip comprises an n+ type diffusion layer.
Claim 5
Dependent Claim
40 words
The method according to claim 3 wherein each isolation transistor disposed over the first continuous strip is connected to the positive voltage supply and each isolation transistor disposed over the second continuous strip is connected to the negative voltage supply.
Claim 6
Dependent Claim
22 words
The method according to claim 1 wherein the positive voltage supply is five volts and the negative voltage supply is zero volts.
References Cited (Backward Citations)
US4345366A
Cited
US4516312A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |