US4633381A
Expired / Lapsed
US
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Inverter shoot-through protection circuit
Assignee: Sundstrand Corp
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Filing: 1985-02-26
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Granted: 1986-12-30
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Expires: 2005-02-26
Abstract
Abstract Prior circuits for protecting inverter switches from the possibility of overlapping operation which may cause shoot-through have required complex and expensive delay circuits to provide a fixed delay between turn-off of one switch and turn-on of the complementary switch. In order to overcome the problem of complexity and expense, a protection circuit according to the present invention includes a drive signal source for developing complementary first and second drive signals and first and second drive logic circuits coupled to the drive signal source for controlling first and second switching devices, respectively, in response to the drive signals so that overlapping operation is prevented. Each of the drive logic circuit includes an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other drive logic circuit, respectively. The inhibit logic circuit generates a control signal to turn on the respective switching device only when the drive signal is present and the inhibit signal from the other drive logic circuit is not present. Circuits are included for generating the inhibit signal that is coupled to the inhibit logic of the other drive logic circuit, such inhibit signal being generated during the time that the control signal is generated and for a predetermined time period thereafter so that the complementary switch is maintained in an off state until the predetermiend time period has elapsed.
Inventors
- 👤 Anand Upadhyay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:09
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/38
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
181 words
A protection circuit for preventing simultaneous conduction of first and second switching devices having main current path electrodes connected in series across a voltage source, comprising: means for developing complementary first and second drive signals; and first and second means coupled to the drive signal developing means but not coupled to a main current path electrode of either switching device for controlling the first and second switching devices, respectively, in response to the drive signals, each of the controlling means including an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other controlling means, respectively, the inhibit logic circuit generating a control signal to turn on the respective switching device only when the drive signal is present and the inhibit signal from the other controlling means is not present and means for generating the inhibit signal which is coupled to the inhibit logic circuit of the other control means, such inhibit signal being generated during the time that the control signal is generated and for a predetermined time period thereafter.
Claim 2
Dependent Claim
181 words
A protection circuit for preventing simultaneous conduction of first and second switching devices having main current path electrodes connected in series across a voltage source, comprising: means for developing complementary first and second drive signals; and first and second means coupled to the drive signal developing means but not coupled to a main current path electrode of either switching device for controlling the first and second switching devices, respectively, in response to the drive signals, each of the controlling means including an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other controlling means, respectively, the inhibit logic circuit generating a control signal to turn on the respective switching device only when the drive signal is present and the inhibit signal from the other controlling means is not present and means for generating the inhibit signal which is coupled to the inhibit logic circuit of the other control means, such inhibit signal being generated during the time that the control signal is generated and for a predetermined time period thereafter.
Claim 3
Dependent Claim
28 words
The protection circuit of claim 1, wherein the inhibit signal generating means includes a one-shot for developing a pulse of a duration equal to the predetermined time period.
Claim 4
Dependent Claim
33 words
The protection circuit of claim 2, wherein the duration of the pulses developed by the one-shots in the controlling means is equal and greater than the anticipated turn-off times of the switching devices.
Claim 5
Dependent Claim
32 words
The protection circuit of claim 2, wherein the duration of the pulses generated by one of the one-shots is not equal to the duration of the pulses generated by the other one-shot.
Claim 6
Dependent Claim
47 words
The protection circuit of claim 1, wherein each inhibit signal generating means includes a one-shot coupled to the output of the inhibit logic circuit and an OR gate having first and second inputs coupled to the outputs of the other inhibit logic circuit and the one-shot, respectively.
Claim 7
Dependent Claim
28 words
The protection circuit of claim 5, wherein the one-shot develops a pulse of duration T when the output of the inhibit logic circuit drops to a low state.
Claim 8
Dependent Claim
42 words
The protection circuit of claim 1, wherein the inhibit logic circuit includes a NOR gate having an output and first and second inputs which receive an inverted version of the drive signal and the inhibit signal from the other controlling means, respectively.
Claim 9
Dependent Claim
217 words
A protection circuit for preventing simultaneous conduction of first and second switching devices having collector and emitter electrodes connected in series across a voltage source, comprising: means for developing complementary first and second drive signals; and first and second drive logic circuits for controlling the first and second switching devices, respectively, each drive logic circuit being unconnected to the collector or emitter electrodes of the power switches and including an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other drive logic circuit, respectively, the inhibit logic circuit generating a control signal to turn on the respective switching device only when the drive signal coupled thereto is in a high state and the inhibit signal is in a low state, means responsive to a falling edge of the control pulse for generating a pulse of fixed duration T and means coupled to the output of the inhibit logic circuit and the pulse generating means for developing the inhibit signal which is coupled to the inhibit logic circuit in the other drive logic circuit, such inhibit signal being in a high state and thereby preventing conduction of the other switching device until a duration T has passed since the control signal has fallen to a low state.
Claim 10
Dependent Claim
217 words
A protection circuit for preventing simultaneous conduction of first and second switching devices having collector and emitter electrodes connected in series across a voltage source, comprising: means for developing complementary first and second drive signals; and first and second drive logic circuits for controlling the first and second switching devices, respectively, each drive logic circuit being unconnected to the collector or emitter electrodes of the power switches and including an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other drive logic circuit, respectively, the inhibit logic circuit generating a control signal to turn on the respective switching device only when the drive signal coupled thereto is in a high state and the inhibit signal is in a low state, means responsive to a falling edge of the control pulse for generating a pulse of fixed duration T and means coupled to the output of the inhibit logic circuit and the pulse generating means for developing the inhibit signal which is coupled to the inhibit logic circuit in the other drive logic circuit, such inhibit signal being in a high state and thereby preventing conduction of the other switching device until a duration T has passed since the control signal has fallen to a low state.
Claim 11
Dependent Claim
14 words
The protection circuit of claim 8, wherein the developing means is an OR gate.
Claim 12
Dependent Claim
43 words
The protection circuit of claim 8, wherein the inhibit logic circuit includes a NOR gate having an output and first and second inputs which receive an inverted version of the drive signal and the inhibit signal from the other drive logic circuit, respectively.
Claim 13
Dependent Claim
14 words
The protection circuit of claim 8, wherein the pulse generating means comprises a one-shot.
Claim 14
Dependent Claim
14 words
The protection circuit of claim 11, wherein the one-shots develop pulses of equal duration.
Claim 15
Dependent Claim
32 words
The protection circuit of claim 11, wherein the duration of the pulses generated by one of the one-shots is not equal to the duration of the pulses generated by the other one-shot.
Claim 16
Dependent Claim
228 words
A protection circuit for preventing simultaneous conduction of first and second switching devices having main current path electrodes connected in series across a voltage source, comprising: means for developing complementary first and second drive signals; and first and second drive logic circuits for controlling the first and second switching devices, respectively, each drive logic circuit being unconnected to and therefore unresponsive to the current in or voltage of any of the main current path electrodes and including an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other drive logic circuit, respectively, the inhibit logic circuit generating a control signal to turn on the respective switching device only when the drive signal coupled thereto is in a high state and the inhibit signal is in a low state, a one-shot responsive to a falling edge of the control pulse for generating a pulse of fixed duration T and an OR gate having inputs coupled to the output of the inhibit logic circuit and the one-shot for developing the inhibit signal which is coupled to the inhibit logic circuit in the other drive logic circuit, such inhibit signal being in a high state and thereby preventing conduction of the other switching device until the duration T has passed since the control signal has fallen to a low state.
Claim 17
Dependent Claim
228 words
A protection circuit for preventing simultaneous conduction of first and second switching devices having main current path electrodes connected in series across a voltage source, comprising: means for developing complementary first and second drive signals; and first and second drive logic circuits for controlling the first and second switching devices, respectively, each drive logic circuit being unconnected to and therefore unresponsive to the current in or voltage of any of the main current path electrodes and including an inhibit logic circuit having first and second inputs which receive the drive signal and an inhibit signal developed by the other drive logic circuit, respectively, the inhibit logic circuit generating a control signal to turn on the respective switching device only when the drive signal coupled thereto is in a high state and the inhibit signal is in a low state, a one-shot responsive to a falling edge of the control pulse for generating a pulse of fixed duration T and an OR gate having inputs coupled to the output of the inhibit logic circuit and the one-shot for developing the inhibit signal which is coupled to the inhibit logic circuit in the other drive logic circuit, such inhibit signal being in a high state and thereby preventing conduction of the other switching device until the duration T has passed since the control signal has fallen to a low state.
Claim 18
Dependent Claim
43 words
The protection circuit of claim 14, wherein the inhibit logic circuit includes a NOR gate having an output and first and second inputs which receive an inverted version of the drive signal and the inhibit signal from the other drive logic circuit, respectively.
Claim 19
Dependent Claim
14 words
The protection circuit of claim 14, wherein the one-shots develop pulses of equal duration.
Claim 20
Dependent Claim
32 words
The protection circuit of claim 14, wherein the duration of the pulses generated by one of the one-shots is not equal to the duration of the pulses generated by the other one-shot.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |