Patent US4633221A successfully refreshed from Google Patents.
US4633221A
Expired / Lapsed
US
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Dual slope analog-to-digital converter with automatic, short cycle range determination
Assignee: Intersil Corp
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Filing: 1985-10-09
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Granted: 1986-12-30
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Expires: 2005-10-09
Abstract
Abstract A dual slope analog-to-digital converter with automatic short cycle range determination. The time period of the signal integrate phase is adjusted to accommodate different ranges of input signals. Range selection is achieved automatically with the converter switching quickly from one range to another until the right range is found, without the necessity of displaying an "out of range" reading. Normal mode rejection of 60 Hz noise is achieved on all timing ranges.
Inventors
- 👤 Peter D. Bradshaw
- 👤 Lee L. Evans
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:01
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/18; H03M1/181; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
316 words
In a dual slope analog-to-digital converter of the type having an overall conversion cycle which includes an integrate phase during which a capacitor is charged with an unknown current, proportional to an unknown voltage, for a fixed period of time, a deintegrate phase where said capacitor is discharged with a known current for a variable period of time, said unknown voltage being directly proportional to said variable period of time, and an output phase in which a digital output value corresponding to said unknown voltage is output by said converter, and said converter further having means for measuring said variable period of time, a method for determining said unknown voltage comprising the steps of: (a) establishing a plurality of timing ranges, each differing from at least one other by one order of magnitude; (b) using the shortest timing range as the fixed period of time during a first integrate phase; (c) determining, at the end of a first deintegrate phase, whether said variable period of time is greater or less than a predetermined minimum period of time; (d) before the output phase is completed, using the next longer timing range as the fixed period of time during a second integrate phase if said variable period of time at the end of said first deintegrate phase is less than said predetermined minimum period of time; (e) determining, at the end of a second deintegrate phase, whether said variable period of time is greater or less than said predetermined minimum period of time; and (f) repeating steps (d)-(e) for each of said timing ranges until said variable period of time, at the end of a deintegrate phase, is greater than said predetermined minimum period of time; wherein, the shortest timing range resulting in a variable period of time in excess of the predetermined minimum period of time is determined prior to the completion of the overall conversion cycle.
Claim 2
Dependent Claim
316 words
In a dual slope analog-to-digital converter of the type having an overall conversion cycle which includes an integrate phase during which a capacitor is charged with an unknown current, proportional to an unknown voltage, for a fixed period of time, a deintegrate phase where said capacitor is discharged with a known current for a variable period of time, said unknown voltage being directly proportional to said variable period of time, and an output phase in which a digital output value corresponding to said unknown voltage is output by said converter, and said converter further having means for measuring said variable period of time, a method for determining said unknown voltage comprising the steps of: (a) establishing a plurality of timing ranges, each differing from at least one other by one order of magnitude; (b) using the shortest timing range as the fixed period of time during a first integrate phase; (c) determining, at the end of a first deintegrate phase, whether said variable period of time is greater or less than a predetermined minimum period of time; (d) before the output phase is completed, using the next longer timing range as the fixed period of time during a second integrate phase if said variable period of time at the end of said first deintegrate phase is less than said predetermined minimum period of time; (e) determining, at the end of a second deintegrate phase, whether said variable period of time is greater or less than said predetermined minimum period of time; and (f) repeating steps (d)-(e) for each of said timing ranges until said variable period of time, at the end of a deintegrate phase, is greater than said predetermined minimum period of time; wherein, the shortest timing range resulting in a variable period of time in excess of the predetermined minimum period of time is determined prior to the completion of the overall conversion cycle.
Claim 3
Dependent Claim
36 words
The method of claim 1 further comprising the step of: (g) indicating the value of the unknown voltage from the measured variable period of time when it is greater than said predetermined minimum period of time.
Claim 4
Dependent Claim
241 words
In a dual slope analog to digital converter of the type having an overall conversion cycle which includes a short conversion cycle which includes an integrate phase during which a capacitor is charged with an unknown current, proportional to an unknown voltage, for a fixed period of time, and a deintegrate phase after the integrate phase where said capacitor is discharged with a known current for a variable period of time, said unknown voltage being directly proportional to said variable period of time, said overall conversion cycle further including an output phase in which a digital value corresponding to said unknown voltage is output by said converter, and said converter further having means for measuring said variable period of time, the improvement comprising: timing means for timing one of a plurality of selectable fixed periods of time of unequal duration, each of said fixed periods of time defining a selectable timing range for the integrate phase of a conversion cycle; comparison means for comparing the measured variable time period of each deintegrate phase to a predetermined minimum period; and control means for successively repeating the short conversion cycle for each timing range before the initiation of the output phase and until the measured variable time period exceeds the predetermined minimum period, said control means including means for selecting a timing range for each short conversion cycle so that the next longer timing range is used for each succeeding short conversion cycle.
Claim 5
Dependent Claim
241 words
In a dual slope analog to digital converter of the type having an overall conversion cycle which includes a short conversion cycle which includes an integrate phase during which a capacitor is charged with an unknown current, proportional to an unknown voltage, for a fixed period of time, and a deintegrate phase after the integrate phase where said capacitor is discharged with a known current for a variable period of time, said unknown voltage being directly proportional to said variable period of time, said overall conversion cycle further including an output phase in which a digital value corresponding to said unknown voltage is output by said converter, and said converter further having means for measuring said variable period of time, the improvement comprising: timing means for timing one of a plurality of selectable fixed periods of time of unequal duration, each of said fixed periods of time defining a selectable timing range for the integrate phase of a conversion cycle; comparison means for comparing the measured variable time period of each deintegrate phase to a predetermined minimum period; and control means for successively repeating the short conversion cycle for each timing range before the initiation of the output phase and until the measured variable time period exceeds the predetermined minimum period, said control means including means for selecting a timing range for each short conversion cycle so that the next longer timing range is used for each succeeding short conversion cycle.
Claim 6
Dependent Claim
22 words
The converter of claim 3 wherein each timing range differs from at least one other timing range by one order of magnitude.
Claim 7
Dependent Claim
19 words
The converter of claim 3 wherein each of said timing ranges is defined by fixed number of clock pulses.
Claim 8
Dependent Claim
19 words
The converter of claim 5 wherein the timing ranges are defined by 10, 100, 1000 and 10,000 clock pulses.
Claim 9
Dependent Claim
283 words
In a dual slope analog to digital converter circuit of the type having a conversion cycle which includes an integrate phase during which the capacitor is charged with an unknown current, proportional to an unknown voltage, for a timing range of a predetermined number of clock pulses, and a deintegrate phase after the integrate phase, where said capacitor is discharged with a known current for a variable number of clock pulses, said unknown voltage being directly proportional to said variable number of clock pulses, an output phase in which a digital output value corresponding to said unknown voltage is output by said converter, and said converter further having means for counting said variable number of clock pulses up to a predetermined maximum number of clock pulses, the improvement comprising: timing means for timing one of a plurality of selectable timing ranges of different predetermined numbers of clock pulses wherein the period of one timing range is equal to the period of one cycle of a predetermined frequency signal; comparison means for comparing the counted variable number of clock pulses of each deintegrate phase to a predetermined minimum number of clock pulses; control means for successively repeating the conversion cycle for each timing range before the initiation of the output phase and until the counted variable number of clock pulses exceeds the predetermined minimum number, said control means including means for selecting a timing range for each conversion cycle so that the next longer timing range is used for each succeeding conversion cycle, and means for spreading the predetermined number of pulses evenly throughout said period of one cycle of said predetermined frequency signal for all timing ranges shorter than said one timing range.
Claim 10
Dependent Claim
283 words
In a dual slope analog to digital converter circuit of the type having a conversion cycle which includes an integrate phase during which the capacitor is charged with an unknown current, proportional to an unknown voltage, for a timing range of a predetermined number of clock pulses, and a deintegrate phase after the integrate phase, where said capacitor is discharged with a known current for a variable number of clock pulses, said unknown voltage being directly proportional to said variable number of clock pulses, an output phase in which a digital output value corresponding to said unknown voltage is output by said converter, and said converter further having means for counting said variable number of clock pulses up to a predetermined maximum number of clock pulses, the improvement comprising: timing means for timing one of a plurality of selectable timing ranges of different predetermined numbers of clock pulses wherein the period of one timing range is equal to the period of one cycle of a predetermined frequency signal; comparison means for comparing the counted variable number of clock pulses of each deintegrate phase to a predetermined minimum number of clock pulses; control means for successively repeating the conversion cycle for each timing range before the initiation of the output phase and until the counted variable number of clock pulses exceeds the predetermined minimum number, said control means including means for selecting a timing range for each conversion cycle so that the next longer timing range is used for each succeeding conversion cycle, and means for spreading the predetermined number of pulses evenly throughout said period of one cycle of said predetermined frequency signal for all timing ranges shorter than said one timing range.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |