Analog-to-digital converter

Claim 2

An analog-to-digital converter comprising: an integrator having first and second inputs and powered from first and second potentials for integrating a difference between input voltages applied to said first and second inputs, said first input being supplied with a medium voltage between a first reference voltage and a second reference voltage of which the magnitude is larger than the first reference voltage; a comparator powered from said first and second potentials for comparing the output voltage of said integrator with a comparison reference voltage, the magnitude of the comparison reference voltage ranging between said first and second potentials; switching means connected to said second input of said integrator and selectively applying said first reference voltage, said second reference voltage, and an unknown analog signal to said second input of said integrator; means for setting the output of said integrator to the level of said comparison reference voltage at the start of an integrating operation; clock means for producing clock pulses and timing control pulses at predetermined time intervals from the point of time that said integrator commences its integration operation; means for causing said switching means to couple said second reference voltage to said second input of said integrator during a first period with a given duration, said first period terminating upon occurrence of a first timing control pulse; means responsive to the occurrence of said first timing control pulse to cause said switching means to couple said unknown analog signal to said second input of said integrator during a second period, said second period terminating when the output voltage of said integrator reaches said comparison reference voltage when said unknown analog signal is smaller in magnitude than said first reference voltage and upon occurrence of a second timing control pulse when said unknown analog signal is larger in magnitude than said first reference voltage; means responsive to the occurrence of said second timing control pulse to cause said switching means to couple said first reference voltage to said second input of said integrator during a third period, said third period terminating when the output voltage of said integrator equals said comparison reference level; first counting means for counting the number of clock pulses occurring during said third period to provide a digital value corresponding to said unknown analog signal; and second counting means for counting, when said unknown analog signal is smaller than the first reference voltage, the clock pulses occurring during a time interval in said second period from the time the output voltage of said integrator reaches said comparison reference voltage level to the time said second timing control pulse occurs to provide a digital value corresponding to the difference between said unknown analog signal and said first reference voltage.

Claim 3

An analog-to-digital converter according to claim 1, in which said first and second reference voltages are equal to said first and second potentials for said integrator, respectively.

Claim 4

An analog-to-digital converter according to claim 1 or 2, in which said first reference voltage is ground voltage.

Claim 5

An analog-to-digital converter according to claim 1, in which said means for conditioning said integrator to initiate its integration operation from said comparison reference voltage level is porvided with means for operating said integrator as a voltage follower before said integration operation is started.

Claim 6

An analog to digital converter according to claim 1, in which the polarity of said unknown analog signal is the same as that of said second reference voltage considered with respect to said first reference voltage.

Claim 7

An analog-to-digital converter comprising: an integrator having first and second inputs and powered from first and second potentials for integrating a difference between input voltages applied to said first and second inputs, said first input being supplied with a medium voltage between a first reference voltage and a second reference voltage of which the magnitude is larger than said first reference voltage; a comparator powered from said first and second potentials for comparing the output voltage of said integrator with a comparison reference voltage, the magnitude of said comparison reference voltage ranging between said first and second potentials; switching means connected to said second input of said integrator and selectively applying said first reference voltage, said second reference voltage, and an unknown analog signal to said second input of said integrator; means for setting the output of said integrator to the level of said comparison reference voltage at the start of an integrating operation; clock means for producing clock pulses and timing control pulses at predetermined time intervals from the point of time that said integrator commences its integration operation; means for causing said switching means to couple said second reference voltage to said second input of said integrator during a first period with a given duration, said first period terminating upon occurrence of a first timing control pulse; means responsive to the occurrence of said first timing control pulse to cause said switching means to couple said unknown analog signal to said second input of said integrator during a second period, said second period termininating upon occurrence of a second timing control pulse; means responsive to the occurrence of said second timing control pulse to cause said switching means to couple said first reference voltage to said second input of said integrator during a third period, said third period terminating when the output voltage of said integrator equals said comparison reference level; first counting means for counting the number of clock pulses occurring during said third period to provide a digital value corresponding to said unknown analog signal; and second counting means for counting, when said unknown analog signal is larger than said second reference voltage, the clock pulses occurring during a time interval in said third period from the time that a third timing control pulse occurs to the time that the output voltage of said integrator reaches said comparison reference level, to provide a digital value corresponding to the difference between the magnitude of said unknown analog signal and that of said second reference voltage.

Claim 8

An analog-to-digital converter comprising: an integrator having first and second inputs and powered from first and second potentials for integrating a difference between input voltages applied to said first and second inputs, said first input being supplied with a medium voltage between a first reference voltage and a second reference voltage of which the magnitude is larger than said first reference voltage; a comparator powered from said first and second potentials for comparing the output voltage of said integrator with a comparison reference voltage, the magnitude of said comparison reference voltage ranging between said first and second potentials; switching means connected to said second input of said integrator and selectively applying said first reference voltage, said second reference voltage, and an unknown analog signal to said second input of said integrator; means for setting the output of said integrator to the level of said comparison reference voltage at the start of an integrating operation; clock means for producing clock pulses and timing control pulses at predetermined time intervals from the point of time that said integrator commences its integration operation; means for causing said switching means to couple said second reference voltage to said second input of said integrator during a first period with a given duration, said first period terminating upon occurrence of a first timing control pulse; means responsive to the occurrence of said first timing control pulse to cause said switching means to couple said unknown analog signal to said second input of said integrator during a second period, said second period termininating upon occurrence of a second timing control pulse; means responsive to the occurrence of said second timing control pulse to cause said switching means to couple said first reference voltage to said second input of said integrator during a third period, said third period terminating when the output voltage of said integrator equals said comparison reference level; first counting means for counting the number of clock pulses occurring during said third period to provide a digital value corresponding to said unknown analog signal; and second counting means for counting, when said unknown analog signal is larger than said second reference voltage, the clock pulses occurring during a time interval in said third period from the time that a third timing control pulse occurs to the time that the output voltage of said integrator reaches said comparison reference level, to provide a digital value corresponding to the difference between the magnitude of said unknown analog signal and that of said second reference voltage.

Claim 9

An analog-to-digital converter comprising: integrating means having first and second inputs, said second input being connected to an integrating resistance; a first switch for selectively coupling a first reference voltage to said integrating resistance to apply said voltage to said integrating means through said resistance; a second switch for selectively coupling a second reference voltage to said integrating resistance to apply said voltage to said integrating means; a third switch for selectively coupling an unknown voltage to said integrating resistance to apply said voltage to said integrating means; means for applying a reference voltage having a magnitude between said first and second reference voltages to said first input of said integrating means; voltage comparator means coupled to the output of said integrating means and including means for establishing a threshold voltage lying between said first and second reference voltages, said comparator means being constructed and arranged to produce an output signal when the output of said integrating means equals said threshold voltage; a source of clock pulses; control means responsive to said clock signals and to said comparator output signal for generating a series of timing signals to close said switches in a non-overlapping sequence such that said reference voltages and said unknown voltage are applied to said integrating means in a predetermined order during an A/D conversion cycle, said sequence comprising (1) the closing of said first switch for a first interval terminated by the occurrence of said comparator output signal whereby said first reference voltage is integrated to set the output of said integrating means to said threshold voltage, (2) the closing of said second switch for a second interval to set the output of said integrating means to a voltage intermediate said first and second reference voltages, (3) the closing of said third switch for a third interval to integrate said unknown voltage, and (4) the closing of said first switch for a fourth interval terminated by the occurrence of said comparator output signal, whereby the output of said integrating means is returned to said threshold voltage; output means for timing the duration of said fourth interval to produce a digital output representing the magnitude of said unknown voltage; further means included in said control means for generating a control pulse when a comparator output signal is produced while said third switch is closed, said control pulse operating to open said third switch and to inhibit the reclosing of said first switch; and additional means included in said output means and being responsive to said control pulse for indicating that said unknown voltage is an out of range voltage not falling in the voltage range between said first and second reference voltages and for timing the duration of the interval between the occurrence of said control pulse and the termination of a predetermined interval following the start of said third interval, whereby said additional means produces a digital output representing the amount by which said unknown voltage lies outside said voltage range.

Claim 10

An analog-to-digital converter comprising: integrating means having first and second inputs, said second input being connected to an integrating resistance; a first switch for selectively coupling a first reference voltage to said integrating resistance to apply said voltage to said integrating means through said resistance; a second switch for selectively coupling a second reference voltage to said integrating resistance to apply said voltage to said integrating means; a third switch for selectively coupling an unknown voltage to said integrating resistance to apply said voltage to said integrating means; means for applying a reference voltage having a magnitude between said first and second reference voltages to said first input of said integrating means; voltage comparator means coupled to the output of said integrating means and including means for establishing a threshold voltage lying between said first and second reference voltages, said comparator means being constructed and arranged to produce an output signal when the output of said integrating means equals said threshold voltage; a source of clock pulses; control means responsive to said clock signals and to said comparator output signal for generating a series of timing signals to close said switches in a non-overlapping sequence such that said reference voltages and said unknown voltage are applied to said integrating means in a predetermined order during an A/D conversion cycle, said sequence comprising (1) the closing of said first switch for a first interval terminated by the occurrence of said comparator output signal whereby said first reference voltage is integrated to set the output of said integrating means to said threshold voltage, (2) the closing of said second switch for a second interval to set the output of said integrating means to a voltage intermediate said first and second reference voltages, (3) the closing of said third switch for a third interval to integrate said unknown voltage, and (4) the closing of said first switch for a fourth interval terminated by the occurrence of said comparator output signal, whereby the output of said integrating means is returned to said threshold voltage; output means for timing the duration of said fourth interval to produce a digital output representing the magnitude of said unknown voltage; further means included in said control means for generating a control pulse when a comparator output signal is produced while said third switch is closed, said control pulse operating to open said third switch and to inhibit the reclosing of said first switch; and additional means included in said output means and being responsive to said control pulse for indicating that said unknown voltage is an out of range voltage not falling in the voltage range between said first and second reference voltages and for timing the duration of the interval between the occurrence of said control pulse and the termination of a predetermined interval following the start of said third interval, whereby said additional means produces a digital output representing the amount by which said unknown voltage lies outside said voltage range.

Claim 11

An analog-to-digital converter comprising: integrating means having first and second inputs, said second input being connected to an integrating resistance; a first switch for selectively coupling a first reference voltage to said integrating resistance to apply said voltage to said integrating means through said resistance; a second switch for selectively coupling a second reference voltage to said integrating resistance to apply said voltage to said integrating means; a third switch for selectively coupling an unknown voltage to said integrating resistance to apply said voltage to said integrating means; means for applying a reference voltage having a magnitude between said first and second reference voltages to said first input of said integrating means; voltage comparator means coupled to the output of said integrating means and including means for establishing a threshold voltage lying between said first and second reference voltages, said comparator means being constructed and arranged to produce an output signal when the output of said integrating means equals said threshold voltage; a source of clock pulses; control means responsive to said clock signals and to said comparator output signal for generating a series of timing signals to close said switches in a non-overlapping sequence such that said reference voltages and said unknown voltage are applied to said integrating means in a predetermined order during an A/D conversion cycle, said sequence comprising (1) the closing of said first switch for a first interval terminated by the occurrence of said comparator output signal whereby said first reference voltage is integrated to set the output of said integrating means to said threshold voltage, (2) the closing of said second switch for a second interval to set the output of said integrating means to a voltage intermediate said first and second reference voltages, (3) the closing of said third switch for a third interval to integrate said unknown voltage, and (4) the closing of said first switch for a fourth interval terminated by the occurrence of said comparator output signal, whereby the output of said integrating means is returned to said threshold voltage; output means for timing the duration of said fourth interval to produce a digital output representing the magnitude of said unknown voltage; further means included in said control means for generating a control pulse when a comparator output signal fails to occur within a predetermined interval following the start of said fourth interval; and additional means included in said output means and being responsive to said control pulse for indicating that said unknown voltage is an out of range voltage not falling in the voltage range between said first and second reference voltages and for timing the duration of the interval between the occurrence of said control pulse and the termination of said fourth interval, whereby said additional means produces a digital output representing the amount by which said unknown voltage lies outside said voltage range.

Claim 12

An analog-to-digital converter comprising: integrating means having first and second inputs, said second input being connected to an integrating resistance; a first switch for selectively coupling a first reference voltage to said integrating resistance to apply said voltage to said integrating means through said resistance; a second switch for selectively coupling a second reference voltage to said integrating resistance to apply said voltage to said integrating means; a third switch for selectively coupling an unknown voltage to said integrating resistance to apply said voltage to said integrating means; means for applying a reference voltage having a magnitude between said first and second reference voltages to said first input of said integrating means; voltage comparator means coupled to the output of said integrating means and including means for establishing a threshold voltage lying between said first and second reference voltages, said comparator means being constructed and arranged to produce an output signal when the output of said integrating means equals said threshold voltage; a source of clock pulses; control means responsive to said clock signals and to said comparator output signal for generating a series of timing signals to close said switches in a non-overlapping sequence such that said reference voltages and said unknown voltage are applied to said integrating means in a predetermined order during an A/D conversion cycle, said sequence comprising (1) the closing of said first switch for a first interval terminated by the occurrence of said comparator output signal whereby said first reference voltage is integrated to set the output of said integrating means to said threshold voltage, (2) the closing of said second switch for a second interval to set the output of said integrating means to a voltage intermediate said first and second reference voltages, (3) the closing of said third switch for a third interval to integrate said unknown voltage, and (4) the closing of said first switch for a fourth interval terminated by the occurrence of said comparator output signal, whereby the output of said integrating means is returned to said threshold voltage; output means for timing the duration of said fourth interval to produce a digital output representing the magnitude of said unknown voltage; further means included in said control means for generating a control pulse when a comparator output signal fails to occur within a predetermined interval following the start of said fourth interval; and additional means included in said output means and being responsive to said control pulse for indicating that said unknown voltage is an out of range voltage not falling in the voltage range between said first and second reference voltages and for timing the duration of the interval between the occurrence of said control pulse and the termination of said fourth interval, whereby said additional means produces a digital output representing the amount by which said unknown voltage lies outside said voltage range.