US3906486A
Expired / Lapsed
US
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Bipolar dual-ramp analog-to-digital converter
Assignee: Analog Devices Inc
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Filing: 1973-07-02
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Granted: 1975-09-16
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Expires: 1993-07-02
Abstract
Abstract A bipolar dual ramp analog to digital converter, of the type having an analog processing stage for integrating, in succession, an analog input voltage (ramp up) and a reference voltage (ramp down), is characterized by a referencing circuit which develops balanced reference voltages to correspond to either polarity of the analog input voltage. In the referencing circuit, linear elements refer all voltages applied to the analog processing stage to a single reference voltage source. A capacitor couples the analog input voltage to the analog processing stage, and switch means connect the reference voltage source across the capacitor to charge it to the voltage of the source. During the ramp up interval, the analog input voltage is connected in series with the charged capacitor and analog processing stage. Derivative voltages are linearly derived from the reference voltage source by means of conductors or resistive voltage dividers, and during the ramp down interval switch means connect one of the derivative voltages to the analog processing stage to form a first reference voltage when the analog input has one polarity, and connect the other of the derivative voltages in series with the capacitor and the analog processing stage to form a second reference voltage when the analog input has the other polarity.
Inventors
- 👤 Berry W Phillips
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:06
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
337 words
A bipolar dual-ramp analog-to-digital converter of the type arranged to provide a digital output corresponding to the magnitude and polarity of an analog input voltage and including an analog processing stage having an integrator and comparator, the analog input voltage being applied to the integrator for a predetermined interval, and a reference voltage being applied to the integrator thereafter for a digitally measured interval sufficient to restore the integrator to its initial condition, the comparator sensing the return of the integrator to the initial condition and signalling the end of the digitally measured interval, said converter being characterized by a reference circuit connecting the analog input voltage to the analog processing stage and comprising: a capacitor coupling the analog input voltage to the analog processing stage; a reference voltage source; switch means for effecting connections between elements of said referencing circuit; said switch means including means for connecting the reference voltage source to the capacitor to chaRge it to a voltage linearly related to the voltage of the reference voltage source and for thereafter disconnecting the capacitor from the reference voltage source; said switch means including means for connecting the analog input voltage through the capacitor to the integrator during said predetermined interval, said analog input voltage thereby being biased by the capacitor voltage; means for deriving from the reference voltage source a pair of derivative voltages linearly related thereto; said switch means including means for connecting one of the derivative voltages to the analog processing stage to form a first reference voltage when the analog input voltage is of one polarity; and said switch means including means for connecting the other of the derivative voltages, in series with the capacitor, to the analog processing stage to form a second reference voltage when the analog input voltage is of the other polarity; whereby all of the voltages applied to the analog processing stage are directly or linearly referred to a single voltage source and any deviations therein balance one another over the course of an integrating cycle.
Claim 2
Dependent Claim
337 words
A bipolar dual-ramp analog-to-digital converter of the type arranged to provide a digital output corresponding to the magnitude and polarity of an analog input voltage and including an analog processing stage having an integrator and comparator, the analog input voltage being applied to the integrator for a predetermined interval, and a reference voltage being applied to the integrator thereafter for a digitally measured interval sufficient to restore the integrator to its initial condition, the comparator sensing the return of the integrator to the initial condition and signalling the end of the digitally measured interval, said converter being characterized by a reference circuit connecting the analog input voltage to the analog processing stage and comprising: a capacitor coupling the analog input voltage to the analog processing stage; a reference voltage source; switch means for effecting connections between elements of said referencing circuit; said switch means including means for connecting the reference voltage source to the capacitor to chaRge it to a voltage linearly related to the voltage of the reference voltage source and for thereafter disconnecting the capacitor from the reference voltage source; said switch means including means for connecting the analog input voltage through the capacitor to the integrator during said predetermined interval, said analog input voltage thereby being biased by the capacitor voltage; means for deriving from the reference voltage source a pair of derivative voltages linearly related thereto; said switch means including means for connecting one of the derivative voltages to the analog processing stage to form a first reference voltage when the analog input voltage is of one polarity; and said switch means including means for connecting the other of the derivative voltages, in series with the capacitor, to the analog processing stage to form a second reference voltage when the analog input voltage is of the other polarity; whereby all of the voltages applied to the analog processing stage are directly or linearly referred to a single voltage source and any deviations therein balance one another over the course of an integrating cycle.
Claim 3
Dependent Claim
45 words
A bipolar dual ramp analog to digital converter as claimed in claim 1 wherein the deriving means comprises a pair of conductors connected to the terminals of the reference voltage source, whereby the derivative voltages are the voltage of the reference source voltage and ground.
Claim 4
Dependent Claim
67 words
A bipolar dual ramp analog to digital converter as claimed in claim 2 wherein the capacitor is charged to the voltage of the reference voltage source, whereby the first and second reference voltages applied to the analog processing stage are twice the voltage of the reference voltage source, and zero, and whereby the converter has the same transfer characteristics for either polarity of the analog input voltage.
Claim 5
Dependent Claim
43 words
A bipolar dual-ramp analog-to-digital converter as claimed in claim 1 wherein the deriving means comprises voltage-dividing means connected across the reference voltage source to provide at least one of said derivative voltages as a fraction of the voltage of the reference voltage source.
Claim 6
Dependent Claim
261 words
A bipolar dual-ramp analog-to-digital converter of the type arranged to provide a digital output corresponding to the magnitude and polarity of an analog input voltage by means of an analog processing stage having an integrator and comparator, the analog input voltage being applied to the integrator for a predetermined interval, and a reference voltage being applied to the integrator thereafter for a digitally measured interval to restore the integrator to its initial condition, the comparator sensing the return of the integrator to the initial condition and signalling the end of the digitally measured interval, said converter being characterized by a referencing circuit connecting the analog input voltage to the analog processing stage and comprising: a first voltage input terminal; a second voltage input terminal; a capacitor coupling the first voltage input terminal to the analog processing stage; switch means; said switch means including means for connecting the voltage at the second voltage input terminal to the capacitor to charge it to a voltage linearly related thereto and for thereafter disconnecting the capacitor from the voltage at the second voltage input terminal; means for deriving from the voltage at the second voltage input terminal a pair of derivative voltages linearly related thereto; said switch means including means for connecting one of the derivative voltages to the analog processing stage when the analog input voltage is of one polarity; and said switch means including means for connecting the other of the derivative voltages, in series with the capacitor, to the analog processing stage when the analog input voltage is of the other polarity.
Claim 7
Dependent Claim
261 words
A bipolar dual-ramp analog-to-digital converter of the type arranged to provide a digital output corresponding to the magnitude and polarity of an analog input voltage by means of an analog processing stage having an integrator and comparator, the analog input voltage being applied to the integrator for a predetermined interval, and a reference voltage being applied to the integrator thereafter for a digitally measured interval to restore the integrator to its initial condition, the comparator sensing the return of the integrator to the initial condition and signalling the end of the digitally measured interval, said converter being characterized by a referencing circuit connecting the analog input voltage to the analog processing stage and comprising: a first voltage input terminal; a second voltage input terminal; a capacitor coupling the first voltage input terminal to the analog processing stage; switch means; said switch means including means for connecting the voltage at the second voltage input terminal to the capacitor to charge it to a voltage linearly related thereto and for thereafter disconnecting the capacitor from the voltage at the second voltage input terminal; means for deriving from the voltage at the second voltage input terminal a pair of derivative voltages linearly related thereto; said switch means including means for connecting one of the derivative voltages to the analog processing stage when the analog input voltage is of one polarity; and said switch means including means for connecting the other of the derivative voltages, in series with the capacitor, to the analog processing stage when the analog input voltage is of the other polarity.
Claim 8
Dependent Claim
39 words
A bipolar dual ramp analog to digital converter as claimed in claim 5 wherein the analog input voltage is applied tO the first voltage input terminal and a reference voltage source is applied to the second voltage input terminal.
Claim 9
Dependent Claim
346 words
In a dual-slope analog-to-digital converter wherein a sample voltage to be converted is applied to an integrator circuit to alter the charge on an integrating capacitor away from a datum level at a rate corresponding to the magnitude of the sample voltage, and wherein a D.C. reference signal is subsequently connected to the integrator circuit to alter the charge on the integrating capacitor reversely towards the datum level at a rate corresponding to the magnitude of the reference signal while a digital output signal is developed in accordance with the time required to reach a predetermined integrator circuit level related to said datum level; the method of making such conversion for sample signals of either polarity, comprising the steps of: A. connecting the reference signal source to a ground-isolatable storage device to store therein a signal proportional to the reference signal magnitude; B. applying to the input of said integrator circuit for a first interval of time a net signal corresponding to the sum of said sample voltage and said stored signal; C. biasing said integrator during said first time interval by a voltage which opposes and cancels the component of said net signal which corresponds to said stored signal, whereby the resulting applied voltage to said integrator will alter the charge of said integrator capacitor away from said datum level at a rate determined solely by the sample voltage magnitude; D. determining the polarity of the integrator circuit output produced by the application of said net sample signal thereto; and E. during a second interval of time, and while said integrator remains biased as in step (C), altering the charge on said capacitor back towards said datum level at a predetermined rate by applying to the input of said integrator circuit, selectively in response to the preceding (step D) determination of polarity, either: (1) a first voltage developed from the output of said reference signal source added to said stored signal from said storage device, or (2) a second voltage developed from said storage device without addition of a signal from said reference signal source.
Claim 10
Dependent Claim
346 words
In a dual-slope analog-to-digital converter wherein a sample voltage to be converted is applied to an integrator circuit to alter the charge on an integrating capacitor away from a datum level at a rate corresponding to the magnitude of the sample voltage, and wherein a D.C. reference signal is subsequently connected to the integrator circuit to alter the charge on the integrating capacitor reversely towards the datum level at a rate corresponding to the magnitude of the reference signal while a digital output signal is developed in accordance with the time required to reach a predetermined integrator circuit level related to said datum level; the method of making such conversion for sample signals of either polarity, comprising the steps of: A. connecting the reference signal source to a ground-isolatable storage device to store therein a signal proportional to the reference signal magnitude; B. applying to the input of said integrator circuit for a first interval of time a net signal corresponding to the sum of said sample voltage and said stored signal; C. biasing said integrator during said first time interval by a voltage which opposes and cancels the component of said net signal which corresponds to said stored signal, whereby the resulting applied voltage to said integrator will alter the charge of said integrator capacitor away from said datum level at a rate determined solely by the sample voltage magnitude; D. determining the polarity of the integrator circuit output produced by the application of said net sample signal thereto; and E. during a second interval of time, and while said integrator remains biased as in step (C), altering the charge on said capacitor back towards said datum level at a predetermined rate by applying to the input of said integrator circuit, selectively in response to the preceding (step D) determination of polarity, either: (1) a first voltage developed from the output of said reference signal source added to said stored signal from said storage device, or (2) a second voltage developed from said storage device without addition of a signal from said reference signal source.
Claim 11
Dependent Claim
37 words
The method of claim 7, wherein the bias on said integrator is developed as a voltage on a storage capacitor connected to one terminal of said integrator and provides a voltage component compensating for offset voltage drift.
Claim 12
Dependent Claim
37 words
The method of claim 8, wherein said storage capacitor is charged up to said bias voltage during a step preceding step (B) through the application to said integrator of a voltage derived from said reference signal source.
Claim 13
Dependent Claim
289 words
A bipolar dual-ramp analog-to-digital converter comprising: an integrator; a voltage source providing a first reference voltage; first and second capacitors; switch means for establishing interconnections in a controllable sequence; said switch means including first means for connecting said voltage source to said first capacitor to store therein a signal voltage proportional to that of the voltage source and defining a second reference voltage; means connecting said second capacitor to the input of said integrator to apply a bias voltage thereto; said switch means including second means to store in said second capacitor a bias voltage derived from said voltage source; said switch means including third means operable during a first time interval to connect an applied input voltage in series with said first capacitor to develop a net operating voltage for said integrator, the component of said net operating voltage derived from said first capacitor opposing and cancelling the bias voltage of said second capacitor, whereby said integrator ramps from a datum level at a rate determined solely by the magnitude of said applied input voltage and in a direction determined by the polarity thereof; means for sensIng the polarity of the integrator output with respect to said datum level; and said switch means including fourth means, operable after said first time interval and under the control of said sensing means, to: (1) connect to the input of said integrator a first voltage formed from the series addition of said first and second reference voltages when the integrator output is of one predetermined polarity, and (2) connect to the input of said integrator a second voltage derived from one of said first and second reference voltages when said integrator output is of a polarity opposite to said one polarity.
Claim 14
Dependent Claim
289 words
A bipolar dual-ramp analog-to-digital converter comprising: an integrator; a voltage source providing a first reference voltage; first and second capacitors; switch means for establishing interconnections in a controllable sequence; said switch means including first means for connecting said voltage source to said first capacitor to store therein a signal voltage proportional to that of the voltage source and defining a second reference voltage; means connecting said second capacitor to the input of said integrator to apply a bias voltage thereto; said switch means including second means to store in said second capacitor a bias voltage derived from said voltage source; said switch means including third means operable during a first time interval to connect an applied input voltage in series with said first capacitor to develop a net operating voltage for said integrator, the component of said net operating voltage derived from said first capacitor opposing and cancelling the bias voltage of said second capacitor, whereby said integrator ramps from a datum level at a rate determined solely by the magnitude of said applied input voltage and in a direction determined by the polarity thereof; means for sensIng the polarity of the integrator output with respect to said datum level; and said switch means including fourth means, operable after said first time interval and under the control of said sensing means, to: (1) connect to the input of said integrator a first voltage formed from the series addition of said first and second reference voltages when the integrator output is of one predetermined polarity, and (2) connect to the input of said integrator a second voltage derived from one of said first and second reference voltages when said integrator output is of a polarity opposite to said one polarity.
Claim 15
Dependent Claim
22 words
Apparatus as claimed in claim 10, including a buffer amplifier connected between said first capacitor and one input terminal of said integrator.
Claim 16
Dependent Claim
105 words
Apparatus as claimed in claim 11, wherein said second capacitor is connected between the other input terminal of said integrator and a circuit ground point; and drift-correct circuit means including means to connect said voltage source to the input of said buffer amplifier to apply a corresponding voltage to said one integrator input terminal, said circuit means further including means to apply a negative feedback signal from the output of said integrator to said other integrator input terminal, the negative feedback action serving to charge up said second capacitor to a bias level corresponding to the voltage then applied to said one integrator input terminal.
References Cited (Backward Citations)
US3750146A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |