Error correction for an integrating analog to digital converter

Claim 2

In an analog to digital converter comprising at least a first input amplifier having a gain K1 and having as an input a known voltage Eref and providing an output of - K1 Eref, a second input amplifier having a gain K2 and having as an input an unknown voltage Ex and providing an output K2 Ex where K1 and K2 are nominally equal but differ due to component tolerances, an integrator, means to cause said output K2 Ex to be integrated for a fixed time period T and thereafter said output -K1 Eref to be integrated, means to detect the output of said integrator crossing zero, and means to store in digital from the time t, required for said voltage -K1 Eref to cause said integrator to cross zero said time, t, being equal to K1Ex T/K2 Eref from which Ex may be found, a method of eliminating the scale factor error K1 comprising: a. providing, prior to conversion of Ex and Eref, a test voltage Etest to each of the first and second amplifiers; b. providing the output -K1 Etest of said first amplifier to said integrator for a fixed time period T; c. providing the output K2 Etest of said second amplifier to said integrator to integrate it back to zero; d. measuring and storing the time t1 required to integrate back to zero whereby t1 will equal K2 T/K1; e. using the value of t1 in place of T when performing the integration of K2 Ex whereby the value t2 of t will now equal K1ExK2/K2ErefK1 T or Ex T/Eref thereby causing the error K1/K2 to be cancelled.

Claim 3

The invention according to claim 1 wherein said time T is obtained by counting down a counter having the digital equivalent of T stored therein and said value t1 is obtained by counting up a counter from the time of providing the voltage K2 Etest to the integrator until zero is crossed.

Claim 4

In an analog to digital converter comprising at least a first amplifier having a gain K1 and having as an input a known voltage Eref and providing an output of - K1 Eref a second input amplifier having a gain K2 and having as an input an unknown voltage Ex and providing an output K2 Ex where K1 and K2 are nominally equal but differ due to component tolerances, an integrator, means to cause said output K2 Ex to be integrated for a fixed time period T aNd thereafter said output -K1 Eref to be integrated, means to detect the output of said integrator crossing zero, and means to store in digital from the time t, required for said voltage -K1 Eref to cause said integrator to cross zero said time, t, being equal to K1Ex T/K2 Eref from which Ex may be found, an apparatus for eliminating the scale factor error K1/K2 comprising: a. a voltage source, Etest; b. means to couple said source to each of the first and second amplifiers; c. means to couple the output, -K1 Etest, of the first amplifier to the integrater for a fixed time T; d. means to couple the output K2 Etest of the second amplifier to said integrator after said time, T; e. a counter; f. a clock; g. means to provide the output of said clock to said counter upon the output of said second amplifier being provided to said integrator; h. means to disconnect said clock from said counter upon the sensing of the detecting means of a zero crossing; and i. means to provide the value stored in said counter as the fixed time for the integration of K2 Ex.

Claim 5

In an analog to digital converter comprising at least a first amplifier having a gain K1 and having as an input a known voltage Eref and providing an output of - K1 Eref a second input amplifier having a gain K2 and having as an input an unknown voltage Ex and providing an output K2 Ex where K1 and K2 are nominally equal but differ due to component tolerances, an integrator, means to cause said output K2 Ex to be integrated for a fixed time period T aNd thereafter said output -K1 Eref to be integrated, means to detect the output of said integrator crossing zero, and means to store in digital from the time t, required for said voltage -K1 Eref to cause said integrator to cross zero said time, t, being equal to K1Ex T/K2 Eref from which Ex may be found, an apparatus for eliminating the scale factor error K1/K2 comprising: a. a voltage source, Etest; b. means to couple said source to each of the first and second amplifiers; c. means to couple the output, -K1 Etest, of the first amplifier to the integrater for a fixed time T; d. means to couple the output K2 Etest of the second amplifier to said integrator after said time, T; e. a counter; f. a clock; g. means to provide the output of said clock to said counter upon the output of said second amplifier being provided to said integrator; h. means to disconnect said clock from said counter upon the sensing of the detecting means of a zero crossing; and i. means to provide the value stored in said counter as the fixed time for the integration of K2 Ex.

Claim 6

The invention according to claim 3 wherein said means to couple said voltage source, means to couple said first amplifier, and means to couple said second amplifier comprise: a. a first switch having as inputs Etest and Eref and providing its output to said first amplifier; b. a second switch having as inputs Etest and Ex and providing its output to said second amplifier; c. a third switch coupling said first amplifier to said integrator; d. a fourth switch coupling said second amplifier to said integrator; and e. timing means having a first output coupled to said first and second switches which when present will couple Etest as the respective outputs of said first and second switches and when absent will couple -Eref and Ex as the respective outputs of said first and second switches, said first output being present and absent for alternate essentially equal time periods, a second output coupled to said third switch and adapted to be present closing said switch approximately the first half of the time said first ouptut is present and the second half of the time said first output is absent said third switch being open at all other times, and a third output coupled to said fourth switch adapted to close said fourth switch during the time periods when said third switch is open.

Claim 7

The invention according to claim 4 wherein said means to provide the output of said clock and the means to disconnect said clock comprise start - stop logic having as inputs said third timing output signal and the output the zero crossover detector and responsive to the beginning of said third signal to couple said clock and to the output of said zero crossover detector to disconnect said clock.

Claim 8

In an analog to digital converter comprising at least a first input amplifier providing an unknown voltage, a second input amplifier providing a known voltage, an integrator, means to cause the output of a first amplifier to be integrated by said integrator for a fixed time period and then to integrate the output of said second amplifier in an opposite direction, means to detect said integrator crossing zero and means to store in digital form the time of said integration to zero, apparatus to correct for errors resulting from said first and second amplifiers having different gains comprising, means to perform a test conversion prior to each unknown conversion to develop a correction factor in the form of a time value to be used in the first integration during the unknown conversion.

Claim 9

In an analog to digital converter comprising at least a first input amplifier providing an unknown voltage, a second input amplifier providing a known voltage, an integrator, means to cause the output of a first amplifier to be integrated by said integrator for a fixed time period and then to integrate the output of said second amplifier in an opposite direction, means to detect said integrator crossing zero and means to store in digital form the time of said integration to zero, apparatus to correct for errors resulting from said first and second amplifiers having different gains comprising, means to perform a test conversion prior to each unknown conversion to develop a correction factor in the form of a time value to be used in the first integration during the unknown conversion.

Claim 10

The invention according to claim 6 wherein said means to perform said test conversion comprise: means to provide a test voltage to each of said first and second ampLifiers; means to invert the sequence of providing outputs of said first and second amplifiers to said integrator and means to store the time obtained during the second integration for use in the unknown conversion.