Integrating antilog function generator

Claim 2

An integrating antilog function generator comprising an analog-to-digital converter, means for applying an unknown potential to the input of said analog-to-digital converter, said analog-to-digital converter including means for establishing a first time period proportional to the magnitude of said unknown potential, means responsive to said converter for establishing a second time period equal to a fixed time interval minus said first time period, and means responsive to said converter for generating a voltage which exponentially decays from a predetermined value in accordance with the equation V Voe t/RC, where V is the exponentially decaying voltage, Vo is the predetermined value of the provided voltage, t is said second time period, and RC is the time constant determining the rate of decay, the value of V at the end of said second time period being the antilog of said unknown potential.

Claim 3

The integrating antilog function generator of claim 1 further comprising means responsively connected to said means for establishing said second time period for preventing further exponential decay of said decaying voltage at the end of said second time period.

Claim 4

The integrating antilog function generator of claim 1 further comprising means cooperatively associated with said means for generating and responsively connected to said converter for applying said decayed voltage from said means for generating to the input of said analog to digital converter, the converter output being a digital representation of the antilog of said unknown potential.

Claim 5

The integrating antilog function generator of claim 1 further comprising means for inhibiting a digital representation of said unknown potential at the output from said analog-to-digital converter.

Claim 6

The integrating antilog function generator of claim 1 wherein said analog-to-digital converter includes integrating means for generating an output signal proportional to the time integral of an input signal applied thereto, and comparator means responsively connected to said integrating means for providing a first signal at the output thereof when the integrator output signal is above a predetermined threshold level and a second signal when the integrator output signal is below said predetermined threshold level.

Claim 7

The integrating antilog function generator of claim 5 wherein said integrating means comprise an operational amplifier, a feedback capacitor connected between the output and input of said amplifier, and a resistor connected in series with said input of said amplifier.

Claim 8

The integrating antilog function generator of claim 1 wherein said means for generating a voltage include an RC network comprising a resistance and a capacitance.

Claim 9

The integrating antilog function generator of claim 7 further comprising means connected to said resistance for discharging said capacitance from said predetermined initial voltage Vo through said resistance during said second time period.

Claim 10

The integrating antilog function generator of claim 8 wherein said means for discharging include a switch connected in series with said resistance.

Claim 11

The integrating antilog function generator of claim 7 further comprising means cooperatively associated with said RC network for charging said capacitance to said predetermined initial voltage Vo.

Claim 12

The integrating antilog function generator of claim 1 wherein said analog to digital converter includes a pulse generator, a pulse counter connected to said pulse generator, and display means connected to said pulse counter.

Claim 13

The integrating antilog function generator of claim 11 wherein said analog to digital converter further includes integrating means for generating an output signal proportional to the time integral of an input signal applied thereto, and comparator means responsively connected to said integrating means for providing a first signal level at the output thereof when the integrator output signal is above a predetermined threshold level and a second signal level when the integrator output signal is below said predetermined threshold level.

Claim 14

The integrating antilog function generator of claim 12 further comprising means responsively connected to said means for establishing said second time period for preventing further exponential decay of said decaying voltage at the end of said second time period, means for inhibiting a digital representation of said unknown potential at the output from said analog-to-digital converter, and means cooperatively associated with said means for generating a voltage and responsively connected to said converter for applying said decayed voltage from said means for generating a voltage to the input of said integrating means, the converter output being the antilog of said unknown potential and being digitally displayed on said display means.

Claim 15

An integrating antilog function generator comprising pulse generating means for generating a series of equal time pulses, pulse counting means responsively connected to said pulse generating means for producing a digital output signal representative of the number of pulses applied to its input and for providing signals to establish first, second, third, and fourth successive equal fixed time intervals, integrating means for generating an output signal applied thereto, comparator means responsively connected to said integrating means for providing a first signal at the output thereof when the integrator output signal is above a predetermined threshold level and a second signal when the integrator output signal is below said predetermined threshold level, means for applying an unknown potential to the input of said integrating means during said first fixed time interval, means for applying a known potential to the input of said integrating means at the start of said second fixed time interval for a first time period proportional to the magnitude of said unknown potential, an RC network including a resistance and a capacitance having a predetermined time constant, means cooperatively associated with said RC network for charging said capacitance to a predetermined initial voltage Vo, means responsive to said comparator means for exponentially discharging said capacitance from said predetermined initial voltage Vo through said resistance in accordance with the equation V Voe t/RC, where V is the exponentially decaying voltage, t is a second time period equal to said second fixed time interval minus said first time period, and RC is the time constant determining the rate of decay, the value of V at the end of said second time period being the antilog of said unknown potential, means cooperatively associated with said RC network and responsively connected to said pulse counting means for applying said decayed voltage to the input of said integrating means at the start of said third fixed time interval, and means responsive to the output of said comparator for providing a signal to said pulse counting means during said fourth fixed time interval, the corresponding output from said pulse counting means during said fourth fixed time interval being a digital representation of the antilog of said unknown potential.

Claim 16

An integrating antilog function generator comprising pulse generating means for generating a series of equal time pulses, pulse counting means responsively connected to said pulse generating means for producing a digital output signal representative of the number of pulses applied to its input and for providing signals to establish first, second, third, and fourth successive equal fixed time intervals, integrating means for generating an output signal applied thereto, comparator means responsively connected to said integrating means for providing a first signal at the output thereof when the integrator output signal is above a predetermined threshold level and a second signal when the integrator output signal is below said predetermined threshold level, means for applying an unknown potential to the input of said integrating means during said first fixed time interval, means for applying a known potential to the input of said integrating means at the start of said second fixed time interval for a first time period proportional to the magnitude of said unknown potential, an RC network including a resistance and a capacitance having a predetermined time constant, means cooperatively associated with said RC network for charging said capacitance to a predetermined initial voltage Vo, means responsive to said comparator means for exponentially discharging said capacitance from said predetermined initial voltage Vo through said resistance in accordance with the equation V Voe t/RC, where V is the exponentially decaying voltage, t is a second time period equal to said second fixed time interval minus said first time period, and RC is the time constant determining the rate of decay, the value of V at the end of said second time period being the antilog of said unknown potential, means cooperatively associated with said RC network and responsively connected to said pulse counting means for applying said decayed voltage to the input of said integrating means at the start of said third fixed time interval, and means responsive to the output of said comparator for providing a signal to said pulse counting means during said fourth fixed time interval, the corresponding output from said pulse counting means during said fourth fixed time interval being a digital representation of the antilog of said unknown potential.

Claim 17

The integrating antilog function generator of claim 14 further comprising means responsive to said pulse counting means for discontinuing further exponential decay of said decaying voltage at the end of said second time period.

Claim 18

The integrating antilog function generator of claim 15 further comprising a frequency dividing means, the input of which is responsively connected to said pulse counting means.

Claim 19

The integrating antilog function generator of claim 16 wherein said means for providing a signal to said pulse counting means comprise a counter strobe AND gate responsively connected to said comparator and frequency dividing means, and a pulse shaper connected between the output of said counter strobe gate and said pulse counting means, said shaper being adapted to activate said pulse counting means to produce said digital output signal.

Claim 20

The integrating antilog function generator of claim 14 further comprising means for inhibiting a digital representation of said unknown potential at the output from said pulse counting means.

Claim 21

The integrating antilog function generator of claim 14 wherein said integrating means comprise an operational amplifier, a feedback capacitor connected between the output and input of said amplifier, and a resistor connected in series with said input to said amplifier.

Claim 22

The integrating antilog function generator of claim 14 further comprising a frequency dividing means, the input of which is responsively connected to said pulse counting means.

Claim 23

The integrating antilog function generator of claim 20 wherein said frequency dividing means is a flip-flop.

Claim 24

The integrating antilog function generator of claim 14 wherein said means for applying an unknown potential comprise a first switch connected in series with the input to said integrating means, and a first AND gate operatively associated with said first switch and responsively connected to said pulse counting means.

Claim 25

The integrating antilog function generator of claim 22 wherein said means for applying a known potential comprise a second switch connected in series with the input to said integrating means, and a second AND gate operatively associated with said second switch and responsively connected to said pulse counting means and said comparator means.

Claim 26

The integrating antilog function generator of claim 14 wherein said means for discharging said capacitance comprise a third swItch series connected to said resistance, and a third AND gate operatively associated with said third switch and responsively connected to said comparator means.

Claim 27

The integrating antilog function generator of claim 14 wherein said means for applying said decayed voltage to said integrating means comprise a fourth switch series connected between the input to said integrating means and said capacitance, and a fourth AND gate operatively associated with said fourth switch and responsively connected to said pulse counting means.

Claim 28

The integrating antilog function generator of claim 20 wherein said means for providing a signal to said pulse counting means comprise a counter strobe AND gate responsively connected to said comparator and frequency dividing means, and a pulse shaper connected between the output of said counter strobe gate and said pulse counting means, said shaper being adapted to activate said pulse counting means to produce said digital output signal.

Claim 29

The integrating antilog function generator of claim 26 further comprising means responsive to said pulse counting means for discontinuing further exponential decay of said decaying voltage at the end of said second time period.

Claim 30

The integrating antilog function generator of claim 27 wherein said means for applying an unknown potential comprise a first switch connected in series with the input to said integrating means, and a first AND gate operatively associated with said first switch and responsively connected to said pulse counting means, wherein the means for applying a known potential comprise a second switch connected in series with the input to said integrating means, and a second AND gate operatively associated with said second switch and responsively connected to said pulse counting means and said comparator means, wherein said means for discharging said capacitance comprise a third switch series connected to said resistance, and a third AND gate operatively associated with said third switch and responsively connected to said comparator means, and wherein said means for applying said decayed voltage to said integrating means comprise a fourth switch series connected between the input to said integrating means and said capacitance, and a fourth AND gate operatively associated with said fourth switch and responsively connected to said pulse counting means.

Claim 31

An integrating antilog function generator comprising an analog-to-digital converter, means for applying an unknown potential to the input of said analog-to-digital converter, said analog-to-digital converter including means for establishing a first time period proportional to the magnitude of said unknown potential, means responsive to said converter for establishing a second time period equal to a fixed time interval minus said first time period, and means responsive to said converter for providing a voltage in accordance with the equation V Voe t/RC, where V is the value of said voltage at the end of said second time period, Vo is the value of a predetermined constant voltage, t is said second time period, and R and C are constants, the value of V at the end of said second time period being the antilog of said unknown potential.

Claim 32

An integrating antilog function generator comprising an analog-to-digital converter, means for applying an unknown potential to the input of said analog-to-digital converter, said analog-to-digital converter including means for establishing a first time period proportional to the magnitude of said unknown potential, means responsive to said converter for establishing a second time period equal to a fixed time interval minus said first time period, and means responsive to said converter for providing a voltage in accordance with the equation V Voe t/RC, where V is the value of said voltage at the end of said second time period, Vo is the value of a predetermined constant voltage, t is said second time period, and R and C are constants, the value of V at the end of said second time period being the antilog of said unknown potential.