Patent US4633097A successfully refreshed from Google Patents.
US4633097A
Expired / Lapsed
US
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Clock monitor circuit and method
Assignee: Motorola Solutions Inc
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Filing: 1983-11-17
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Granted: 1986-12-30
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Expires: 2003-11-17
Abstract
Abstract A clock monitor circuit and method for providing an indication at the output thereof of the presence of an input clocking signal. If the clock input is operating properly, two charge storage nodes will be charged and the output of the circuit will be high. If the clock input is stuck, the output of the clock monitor circuit will be low.
Inventors
- 👤 B. Chris Dewitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/19
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
254 words
A clock monitor circuit for providing an output signal indicative of the presence of a clock signal which oscillates between first and second predetermined voltage levels, said monitor circuit comprising: first charge storage means; charging means, coupled to said first charge storage means and for receiving said clock signal, said charging means charging said first charge storage means at a first predetermined rate when said clock signal is at said first voltage level; first discharging means, coupled to said first charge storage means, for continuously discharging said first charge storage means at a second predetermined rate which is less than said first predetermined rate; first coupling means for receiving said clock signal and coupled to said first charge storage means, said first coupling means coupling said clock signal to a second node when the voltage on said first charge storage means exceeds a predetermined threshold voltage level; second charge storage means; second coupling means for receiving said clock signal and coupled to said second node, said second coupling means coupling said second node to said second charge storage means when said clock signal is at said second predetermined voltage level, said second charge storage means being charged by said clock signal via said second node; second discharging means, coupled to said second charge storage means, for continuously discharging said second charge storage means at a third predetermined rate independent of said first and second predetermined rates; and buffer means for providing an output signal indicative of the voltage on said second charge storage means.
Claim 2
Dependent Claim
254 words
A clock monitor circuit for providing an output signal indicative of the presence of a clock signal which oscillates between first and second predetermined voltage levels, said monitor circuit comprising: first charge storage means; charging means, coupled to said first charge storage means and for receiving said clock signal, said charging means charging said first charge storage means at a first predetermined rate when said clock signal is at said first voltage level; first discharging means, coupled to said first charge storage means, for continuously discharging said first charge storage means at a second predetermined rate which is less than said first predetermined rate; first coupling means for receiving said clock signal and coupled to said first charge storage means, said first coupling means coupling said clock signal to a second node when the voltage on said first charge storage means exceeds a predetermined threshold voltage level; second charge storage means; second coupling means for receiving said clock signal and coupled to said second node, said second coupling means coupling said second node to said second charge storage means when said clock signal is at said second predetermined voltage level, said second charge storage means being charged by said clock signal via said second node; second discharging means, coupled to said second charge storage means, for continuously discharging said second charge storage means at a third predetermined rate independent of said first and second predetermined rates; and buffer means for providing an output signal indicative of the voltage on said second charge storage means.
Claim 3
Dependent Claim
153 words
A clock monitoring method for providing an output signal indicative of the presence of a clock signal which oscillates between first and second predetermined voltage levels, said method comprising the steps of: charging a first node at a first predetermined rate when said clock signal is at said first voltage level; continuously discharging said first node at a second predetermined rate which is less than said first predetermined rate; coupling said clock signal to a second node when the voltage on said first node exceeds a predetermined threshold voltage level; coupling said second node to a third node when said clock signal is at said second predetermined voltage level, said third node being charged by said clock signal via said second node; continuously discharging said third node at a third predetermined rate independent of said first and second predetermined rates; and providing an output signal indicative of the voltage on said third node.
Claim 4
Dependent Claim
153 words
A clock monitoring method for providing an output signal indicative of the presence of a clock signal which oscillates between first and second predetermined voltage levels, said method comprising the steps of: charging a first node at a first predetermined rate when said clock signal is at said first voltage level; continuously discharging said first node at a second predetermined rate which is less than said first predetermined rate; coupling said clock signal to a second node when the voltage on said first node exceeds a predetermined threshold voltage level; coupling said second node to a third node when said clock signal is at said second predetermined voltage level, said third node being charged by said clock signal via said second node; continuously discharging said third node at a third predetermined rate independent of said first and second predetermined rates; and providing an output signal indicative of the voltage on said third node.
References Cited (Backward Citations)
US3233118A
Cited
US3582676A
Cited
US3624410A
Cited
US4197508A
Cited
US4322642A
Cited
US4345209A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |