US3624410A
Expired / Lapsed
US
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Balanced integrate and dump circuit for measuring duty cycle of a pulse train
Assignee: Motorola Solutions Inc
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Filing: 1969-05-01
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Granted: 1971-11-30
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Expires: 1989-05-01
Abstract
Abstract A balanced integrate and dump circuit includes a first integrator, differential amplifier, second integrator and timing circuit, for detecting the presence or absence of pulse train signals in a predetermined time interval, determining whether the pulse train signals are present for greater than a predetermined percentage of the time interval measured and resetting the circuit for the next measurement. Differential comparison of voltages representing the presence and absence of pulses in the measured time interval eliminates errors due to timing period variations, voltage variations, imperfect pulse train signals and circuit operating characteristics.
Inventors
- 👤 Eugene J Bruckert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:37
CPC Classifications
H; H03; H03K; H03K9/00; H03K9/08
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
221 words
An integrate and dump circuit for measuring the duty cycle of a pulse train, including in combination, input means adapted to receive the pulse train and to develop therefrom first and second trains of pulse signals with said second train of pulse signals being the inverse of said first train of pulse signals, first and second integration means each coupled to said input means and having a transistor biased to conduct in response to a voltage exceeding a predetermined level, timing means coupled to said first and second integration means for developing a timing signal to reset said first and second integration means to a reference voltage after a predetermined time period, said first integration means being responsive to said first train of pulse signals during said predetermined period to develop and maintain a first voltage proportional to the duty cycle of the first train of pulse signals, said second integration means being responsive to said second train of pulse signals during said predetermined period to develop and maintain a second voltage proportional to the duty cycle of the second pulse train, difference comparison means including transistor current limiting means coupled to said first and second integration means and responsive to said first and second voltages to develop a comparison signal indicating which of said first and second voltages is greater.
Claim 2
Dependent Claim
221 words
An integrate and dump circuit for measuring the duty cycle of a pulse train, including in combination, input means adapted to receive the pulse train and to develop therefrom first and second trains of pulse signals with said second train of pulse signals being the inverse of said first train of pulse signals, first and second integration means each coupled to said input means and having a transistor biased to conduct in response to a voltage exceeding a predetermined level, timing means coupled to said first and second integration means for developing a timing signal to reset said first and second integration means to a reference voltage after a predetermined time period, said first integration means being responsive to said first train of pulse signals during said predetermined period to develop and maintain a first voltage proportional to the duty cycle of the first train of pulse signals, said second integration means being responsive to said second train of pulse signals during said predetermined period to develop and maintain a second voltage proportional to the duty cycle of the second pulse train, difference comparison means including transistor current limiting means coupled to said first and second integration means and responsive to said first and second voltages to develop a comparison signal indicating which of said first and second voltages is greater.
Claim 3
Dependent Claim
97 words
The integrate and dump circuit of claim 1 wherein said difference comparison means includes a differential amplifier, said differential amplifier having a first input coupled to said first integration means and a second input coupled to said second integration means, said transistor current limiting means being coupled to said differential amplifier for limiting the current therethrough, said differential amplifier comparing said first and second voltages and developing a signal indiCating which of said first and second voltages is greater, thereby determining whether the duty cycle of the pulse train exceeds a predetermined percentage of the predetermined period.
Claim 4
Dependent Claim
77 words
The integrate and dump circuit of claim 1 wherein said transistors of said first and second integration means each forms current source means responsive to its particular train of pulse signals and including reactance means coupled to said current source means, said current source means and reactance means acting in combination to develop a voltage from said particular train of pulse signals which is a function of the duty cycle of said particular train of pulse signals.
Claim 5
Dependent Claim
89 words
The integrate and dump circuit of claim 1 wherein said transistors of said first and second integration means each forms transistor current source means, each of said transistor current source means having a control electrode adapted to receive said particular train of pulse signals, a capacitor coupled to said transistor current source means, said current source means and capacitor means acting in combination to develop a voltage from said particular train of pulse signals which is a function of the duty cycle of said particular train of pulse signals.
Claim 6
Dependent Claim
100 words
The integrate and dump circuit of claim 1, wherein said timing means includes clock means, a first transistor having a first electrode coupled to said first integration means, a second electrode coupled to a reference potential and a control electrode coupled to said clock means, a second transistor having a first electrode coupled to said second integration means, a second electrode coupled to said reference potential and a control electrode coupled to said clock means, said first and second transistors being responsive to said timing signal to reset said first and second integration means after a predetermined period of time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-29 | 1975-05-31 | 1975-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-29 | 1979-05-31 | 1979-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-29 | 1983-05-31 | 1983-11-30 | $7700.00 | Window Closed / Lapsed |