Dynamic flip-flop with static reset

Claim 1

An asynchronously resettable high-speed dynamic flip-flop comprising: A. a state gate, having an output port and reset and data input ports, for presenting a first, set value at its output port when the values at its input ports, including a latch input port, are all true and for presenting a second, reset value at its output port when at least one of the values at its input ports is false; B. a first transmission gate, having an input port, a clock port, and an output port connected to the data input port of the state gate, for presenting at its output port the value of the signal at its input port when the signal at its clock port has a first, enabling value and for maintaining at the state-gate input ports, while the signal at its clock port has a second, disabling value, the value that the signal at its input port had when the signal at its clock port assumed the disabling value; C. a second transmission gate having a clock port, an output port connected to a capacitive load, and an input port connected to receive the signal at the output port of the state gate, for presenting at its output port the value of the signal at its input port when the signal at its clock port is has a first, enabling value and for maintaining on said capacitive load connected to its output port, while the signal at its clock port has a second, disabling value, the value that the signal at its input port had when the signal at its clock port assumed the disabling value, the flip-flop thereby operating synchronously as a D-type flip-flop when appropriate clock signals are applied to its clock input ports but being asynchronously resettable by application of a false signal to its reset input port; D. a latch gate having a feedback input port connected to receive the state-gate output, the latch gate also having an enable input port and having an output port connected to the latch input port of the state gate, the latch gate presenting at its output port a false value when the signal at its enable port has a first, enable value and the output of the state gate is at its reset value, the output of the latch gate being true when the signal at its enable port has a second, disable value or the output of the state gate is at its set value, the flip-flop, once it has assumed its reset state, remaining in said reset state only so long as the signal at the enable input port has the enable value, and selectively being returned to a state in which the signal on the output port of the flip-flop becomes equal to the signal of the data input to the flip-flop after the flip-flop has been clocked and a suitable propagation time has elapsed upon the signal at the enable input port returning to the disable value.