US4630295A
Expired / Lapsed
US
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Low power consumption CMOS shift register
Assignee: Sharp Corp
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Filing: 1984-07-24
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Granted: 1986-12-16
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Expires: 2004-07-24
Abstract
Abstract A serial input/output device includes a CMOS shift register having a plurality of D-type flip-flops. A detection circuit is associated with the CMOS shift register in order to detect whether the transfer data exists in the CMOS shift register. A gate circuit is provided for applying a transfer clock signal to the CMOS shift register only when the transfer data exists in the CMOS shift register, thereby minimizing the power consumption.
Inventors
- 👤 Setsufumi Kamuro
- 👤 Takaaki Hirano
- 👤 Mikiro Okada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:24
CPC Classifications
G; G11; G11C; G11C19/00; G11C7/00; G11C7/10; G11C7/1015; G11C7/1036
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
122 words
A CMOS shift register system for minimizing power consumption, comprising: a CMOS shift register; detection means for providing a first signal when data meant for transfer exists in said CMOS shift register and a second signal when said shift register is full, said shift register being full being indicative that said shift register does not contain data that are to be transferred; transfer clock generation means for providing a clock signal so as to transfer data in said CMOS shift register; and means for applying said clock signal to said CMOS shift register only in response to said first signal of said detection means and inhibiting further clock signal application in response to said second signal so that power consumption is minimized.
Claim 2
Dependent Claim
122 words
A CMOS shift register system for minimizing power consumption, comprising: a CMOS shift register; detection means for providing a first signal when data meant for transfer exists in said CMOS shift register and a second signal when said shift register is full, said shift register being full being indicative that said shift register does not contain data that are to be transferred; transfer clock generation means for providing a clock signal so as to transfer data in said CMOS shift register; and means for applying said clock signal to said CMOS shift register only in response to said first signal of said detection means and inhibiting further clock signal application in response to said second signal so that power consumption is minimized.
Claim 3
Dependent Claim
133 words
A serial output device in a transmitting system for minimizing power consumption comprising: a CMOS shift register including a plurality of flip-flops, the last flip-flop serially developing transmitting data; transfer clock generation means for providing a clock signal so as to transfer data in said CMOS register; detection means for developing a first signal when data meant for transmission is present is said CMOS shift register and a second signal when said shift register is full which is indicative that said shift register does not contain data that is meant for transmission; and gate means for applying said clock signal to said CMOS shift register in response to said first signal of said detection means and inhibiting further clock signal application in response to said second signal so that power consumption is minimized.
Claim 4
Dependent Claim
133 words
A serial output device in a transmitting system for minimizing power consumption comprising: a CMOS shift register including a plurality of flip-flops, the last flip-flop serially developing transmitting data; transfer clock generation means for providing a clock signal so as to transfer data in said CMOS register; detection means for developing a first signal when data meant for transmission is present is said CMOS shift register and a second signal when said shift register is full which is indicative that said shift register does not contain data that is meant for transmission; and gate means for applying said clock signal to said CMOS shift register in response to said first signal of said detection means and inhibiting further clock signal application in response to said second signal so that power consumption is minimized.
Claim 5
Dependent Claim
27 words
The serial output device of claim 2, further comprising preset means for introducing the data meant for transmitting into said CMOS shift register in a parallel fashion.
Claim 6
Dependent Claim
122 words
A serial input device in a receiver system for minimizing power consumption comprising: a CMOS shift register including a plurality of flip-flops, transfer clock generation means for developing a clock signal so as to transfer data in said CMOS shift register; detection means for providing a first signal when the transmitted data is introduced into said first flip-flop and a second signal when said shift register is full which is indicative that no transmitted data is present in said shift register; and gate means for applying said clock signal to said CMOS register only when said first signal is developed from said detection means and inhibiting further clock signal application in response to said second signal so that power consumption is minimized.
Claim 7
Dependent Claim
122 words
A serial input device in a receiver system for minimizing power consumption comprising: a CMOS shift register including a plurality of flip-flops, transfer clock generation means for developing a clock signal so as to transfer data in said CMOS shift register; detection means for providing a first signal when the transmitted data is introduced into said first flip-flop and a second signal when said shift register is full which is indicative that no transmitted data is present in said shift register; and gate means for applying said clock signal to said CMOS register only when said first signal is developed from said detection means and inhibiting further clock signal application in response to said second signal so that power consumption is minimized.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-15 | 1990-06-16 | 1990-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-15 | 1994-06-16 | 1994-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-15 | 1998-06-16 | 1998-12-16 | $7700.00 | Window Closed / Lapsed |