Manual set system for shift register

Claim 1

In a circuit comprising a clock, and a shift register having a plurality of serially connected flip-flops, each one of said flip-flops including a data input terminal, a clock input terminal, a clear input terminal, a preset input terminal and an output terminal, said clock periodically applying a clock signal to each one of the clock input terminals to pass the signal at the data input terminal to the output terminal of each flip-flop, the improvement comprising: a manually operable switch having a first position for connecting both the clear and the preset input terminals of one of the flip-flops to an activation signal source generating one of a logical 0 signal and a logical 1 signal, said switch having a second position for connecting both the clear and the preset input terminals of said one flip-flop to a deactivation signal source generating the other of said logical 0 signal and said logical 1 signal, at least one electrically conductive component in circuit between said deactivation signal source and one of the clear and the preset input terminals of said one flip-flop for passively delaying initiation of the deactivation signal thereon to latch a logical signal at the output terminal of said one flip-flop when the deactivation signal is developed at the other of the clear and the preset input terminals, said latched logical signal at the output terminal being determined by the activation signal applied to said one of the clear and input terminals when said switch is in said first position, and means responsive to said switch in said first position for disabling said clock to preclude application of clock signals to the clock inputs of the flip-flops.