US4630271A
Expired / Lapsed
US
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Error correction method and apparatus for data broadcasting system
Assignee: Japan Broadcasting Corp
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Filing: 1984-01-17
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Granted: 1986-12-16
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Expires: 2004-01-17
Abstract
Abstract A random multi-error correcting code having a maximum length block in a packet, for instance a majority logic decodable (272, 190) shortened difference set cyclic code, is used for error correction in a character code broadcasting system. The error correcting ability of this code is increased. The correction is made by decreasing a threshold value, so that the error correcting ability is improved. A framing timing extraction circuit and a phase lock circuit for the framing timing are eliminated, so that the amount of hardware needed is reduced. Preferably, the error correcting code is superposed on the television signal during the vertical blanking period.
Inventors
- 👤 Osamu Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:13
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/08; H03; H03M; H03M13/00; H03M13/37; H03M13/43
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
176 words
In a broadcasting system for broadcasting character information in packets having data signal portions of predetermined length, an error correction method for correcting errors included in the broadcasted character information, comprising the steps of: selecting a random multi-error correcting code having a block length that is at least as great as the length of the data signal portion of a packet, and shortening the block length if necessary to fit in the data signal portion of the packet; forming character code signals from said character information; alloting said character code signals sequentially into a plurality of packets, each packet including an allotted character code signal and parity bits determined in accordance with said multi-error correcting code; broadcasting said allotted character code signals and respective parity bits in the data signal portions in the sequence of said packets; receiving the broadcast data signal; multiplying the received data signal portions by a matrix having a predetermined column all consisting of ones to reproduce the character code signal; and decoding the character information from the reproduced character code signal.
Claim 2
Dependent Claim
176 words
In a broadcasting system for broadcasting character information in packets having data signal portions of predetermined length, an error correction method for correcting errors included in the broadcasted character information, comprising the steps of: selecting a random multi-error correcting code having a block length that is at least as great as the length of the data signal portion of a packet, and shortening the block length if necessary to fit in the data signal portion of the packet; forming character code signals from said character information; alloting said character code signals sequentially into a plurality of packets, each packet including an allotted character code signal and parity bits determined in accordance with said multi-error correcting code; broadcasting said allotted character code signals and respective parity bits in the data signal portions in the sequence of said packets; receiving the broadcast data signal; multiplying the received data signal portions by a matrix having a predetermined column all consisting of ones to reproduce the character code signal; and decoding the character information from the reproduced character code signal.
Claim 3
Dependent Claim
80 words
An error correction method as claimed in claim 1, wherein the data signal portion of a packet has a length of 272 bits; wherein the random multi-error correcting code has 273 data-bits consisting of 191 information-bits and 82 parity-bits in the form of a majority logic difference set cyclic code for broadcasting character information; and wherein the random multi-error correcting code is shortened by one information-bit so that 272 data-bits remain to form the data signal portion of a packet.
Claim 4
Dependent Claim
80 words
An error correction method as claimed in claim 1, wherein the data signal portion of a packet has a length of 264 bits; wherein the random multi-error correcting code has 273 data-bits consisting of 191 information-bits and 82 parity-bits in the form of a majority logic difference set cyclic code for broadcasting character information; and wherein the random multi-error correcting code is shortened by nine information-bits so that 264 data-bits remain to form the data signal portion of a packet.
Claim 5
Dependent Claim
154 words
In a broadcasting system having transmitting and receiving sides for respectively transmitting and receiving character information in packets having data signal portions of predetermined length, an error correcting system for correcting errors in a transmission path between said transmitting and receiving sides comprising: in said transmitting side: means for generating a random multi-error correcting code having a block length that is at least as great as the length of the data signal portion of a packet, and for shortening the block length if necessary to fit in the data signal portion of the packet; and means for broadcasting a data signal including at least one packet; and in said receiving side: means for receiving the broadcast data signal; means for multiplying the received data signal by a matrix having a predetermined column all consisting of ones to reproduce a character code signal; and means for decoding character information from the reproduced character code signal.
Claim 6
Dependent Claim
154 words
In a broadcasting system having transmitting and receiving sides for respectively transmitting and receiving character information in packets having data signal portions of predetermined length, an error correcting system for correcting errors in a transmission path between said transmitting and receiving sides comprising: in said transmitting side: means for generating a random multi-error correcting code having a block length that is at least as great as the length of the data signal portion of a packet, and for shortening the block length if necessary to fit in the data signal portion of the packet; and means for broadcasting a data signal including at least one packet; and in said receiving side: means for receiving the broadcast data signal; means for multiplying the received data signal by a matrix having a predetermined column all consisting of ones to reproduce a character code signal; and means for decoding character information from the reproduced character code signal.
Claim 7
Dependent Claim
112 words
An error correcting system as claimed in claim 4, wherein the data signal portion of a packet has a length of 272 bits; wherein said means for generating said random multi-error correcting code comprises means for generating a signal including 273 data-bits consisting of 191 information-bits and 82 parity-bits in the form of a majority logic difference set cyclic code, and means for shortening said signal by one information-bit so that 272 data-bits remain to form the data signal portion of a packet; and wherein said means for broadcasting comprises means for forming as said data signal a plurality of packets, each having 272 data-bits consisting of 190 information-bits and 82 parity-bits.
Claim 8
Dependent Claim
113 words
An error correcting system as claimed in claim 4, wherein the data signal portion of a packet has a length of 264 bits; wherein said means for generating said random multi-error correcting code comprises means for generating a signal including 273 data-bits consisting of 191 information-bits and 82 parity-bits in the form of a majority logic difference set cyclic code, and means for shortening said signal by nine information-bits so that 264 data bits remain to form the data signal portion of a packet; and wherein said means for broadcasting comprises means for forming as said data signal a plurality of packets, each having 264 data-bits consisting of 182 information-bits and 82 parity-bits.
Claim 9
Dependent Claim
114 words
An error correction system as claimed in claim 4, wherein said multiplying means comprises: a syndrome register receiving the data signal portion of a packet for checking a bit error in the data signal portion; a data register receiving the data signal portion of the packet for storing the data signal portion; logic means receiving the output from said syndrome register for delivering a majority decision of said output; means for correcting the leading bit of the output from said data register in accordance with the output from said majority decision logic means; and means for correcting the content of said syndrome register in accordance with the output from said majority decision logic means.
Claim 10
Dependent Claim
89 words
An error correction system as claimed in claim 7, further comprising: means for setting a decision threshold value to said majority decision logic means, said decision threshold value being within the number of input elements to said majority decision logic means; and means for controlling said setting means in such a manner that after all the bits in the data signal portion of one packet are entirely corrected, a predetermined value is sequentially subtracted from said decision threshold value until the decision threshold value reaches a predetermined threshold value.
Claim 11
Dependent Claim
79 words
An error correction system as claimed in claim 8, wherein the data signal portion of a packet has a length of 272 bits and accommodates a 190-bit information signal and an 82-bit parity signal, and wherein the decision threshold value of said majority decision logic means is preset at 17 and said predetermined value that is sequentially subtracted is set at 1, in such a manner that said decision threshold value 17 is sequentially decreased until it reaches 9.
Claim 12
Dependent Claim
25 words
An error correction system as claimed in claim 8, wherein said decision threshold value is set in response to an instruction from an exterior device.
Claim 13
Dependent Claim
29 words
An error correction system as claimed in claim 8, further comprising means for setting said decision threshold value and means for re-loading data read out from said data register.
Claim 14
Dependent Claim
19 words
An error correction system as claimed in claim 8, wherein said decision threshold value is sequentially decreased by 1.
Claim 15
Dependent Claim
23 words
An error correction system as claimed in claim 8, wherein said decision threshold value is sequentially decreased by an integer larger than 1.
Claim 16
Dependent Claim
29 words
An error correction system as defined in claim 8, wherein said decision threshold value is started from an initial value selected from a number group from 9 to 16.
Claim 17
Dependent Claim
70 words
An error correction system as claimed in claim 8, further comprising an error detection circuit including: means for counting the nurber of error correction bits generated from said majority decision logic means during the cyclic correction; and means for deciding that an error is detected when the counted value from said counting means reaches a predetermined value, even if the contents of said syndrome register are all set to zero.
Claim 18
Dependent Claim
24 words
An error detection circuit as claimed in claim 15, wherein said predetermined value is set in response to an instruction from an external device.
Claim 19
Dependent Claim
68 words
An error correction system as defined in claim 7, further comprising a detection circuit including: means for counting the number of error correction bits generated from said majority decision logic means during cyclic correction; and means for deciding that an error is detected when the counted value from said counting means reaches a predetermined value, even if the contents of said syndrome register are all set to zero.
Claim 20
Dependent Claim
78 words
An error correction system as claimed in claim 7, wherein only said syndrome register is shifted bit by bit by the number of bits corresponding to the difference between said block length and the length of the signal data portion of a packet while the output from said majority decision logic means is disabled, and said syndrome register and said data register are shifted when the shift of said syndrome register by said number of bits is completed.
Claim 21
Dependent Claim
45 words
An error correction system as claimed in claim 4, wherein information that could fit within the data signal portion of a single packet is divided into a plurality of groups, each consisting of a plurality of bits, and the groups are allotted into separate packets.
Claim 22
Dependent Claim
50 words
An error correction system as claimed in claim 19, wherein said receiving means comprises means for storing the data signal portions for 34 packets, and a signal which is formatted to accord with the data format on the broadcasting side is written into or read out from said storing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-15 | 1990-06-16 | 1990-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-15 | 1994-06-16 | 1994-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-15 | 1998-06-16 | 1998-12-16 | $7700.00 | Window Closed / Lapsed |